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ORCIDYe Lu 0005
Person information
- affiliation: Fudan University, School of Information Science and Technology, State Key Laboratory of Integrated Chips and Systems, Shanghai, China
- affiliation (2016-2019): Qualcomm, San Diego, CA, USA
- affiliation (2011-2016): Intel Corporation, Hillsboro, OR, USA
- affiliation (PhD 2011): University of Pennsylvania, Philadelphia, PA, USA
Other persons with the same name
- Ye Lu — disambiguation page
- Ye Lu 0001
![[0000-0003-4234-7435]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-4234-7435")
— City University of Hong Kong, Department of Management Sciences - Ye Lu 0002 — Monash University, Department of Civil Engineering, Melbourne, Australia
- Ye Lu 0003 — Queen's University Belfast, UK
- Ye Lu 0004 — Nankai University, College of Computer Science, College of Cyber Science, Tianjin, China
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2020 – today
- 2024
[j4]Yicheng Li, Yun Yin, Diyang Zheng, Fu Gao, Jie Lin, Zhen Hu, Ye Lu, Hongtao Xu:
A Quadrature Digital Power Amplifier With Wide Efficiency Enhancement Coverage and High Dynamic Power Range. IEEE J. Solid State Circuits 59(7): 2133-2144 (2024)- [j3]Jiarui Bao, Jinxin Zhang, Zhangcheng Huang, Zhaori Bi, Xingwei Feng, Xuan Zeng, Ye Lu:
Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4398-4411 (2024) - [c3]Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, Xuan Zeng:
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. ASPDAC 2024: 872-877 - [c2]Handa Sun, Zhaori Bi, Wenning Jiang, Ye Lu, Changhao Yan, Fan Yang, Wenchuang Hu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. DAC 2024: 284:1-284:6 - 2023
- [j2]Xiaona Zhu, Rongzheng Ding, Ouwen Tao, Yage Zhao, Peishun Tang, David Wei Zhang, Ye Lu, Shaofeng Yu:
A Combined N/PFET CFET-Based Design and Logic Technology Framework for CMOS Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4999-5005 (2023) - [c1]Jinxin Zhang, Jiarui Bao, Zhangcheng Huang, Xuan Zeng, Ye Lu:
Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning. DAC 2023: 1-6 - 2022
- [j1]Yicheng Li, Yun Yin, Diyang Zheng, Xianglong Jia, Jie Lin, Fu Gao, Yiting Zhu, Liang Xiong, Na Yan, Ye Lu, Hongtao Xu:
A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement. IEEE J. Solid State Circuits 57(6): 1610-1622 (2022)
Coauthor Index
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