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ORCID29th ASP-DAC 2024: Incheon, Korea
- Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024. IEEE 2024, ISBN 979-8-3503-9355-2
- Tom Glint, Manu Awasthi, Joycee Mekie:
CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs. 1-6 - Zifeng Zhao, Xinghao Zhu, Jiyuan Bai, Gengsheng Chen:
PAIR: Periodically Alternate the Identity of Routers to Ensure Deadlock Freedom in NoC. 7-12 - Fan Jiang, Chengeng Li, Lin Chen, Jiaqi Liu, Wei Zhang, Jiang Xu:
SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating. 13-18 - Chenhui Xu, Fuxun Yu, Zirui Xu, Chenchen Liu, Jinjun Xiong, Xiang Chen:
QuadraNet: Improving High-Order Neural Interaction Efficiency with Hardware-Aware Quadratic Neural Networks. 19-25 - Xiaotian Guo, Quan Jiang, Andy D. Pimentel, Todor P. Stefanov:
RobustDiCE: Robust and Distributed CNN Inference at the Edge. 26-31 - Alessandro Verosimile, Alessandro Tierno, Andrea Damiani, Marco D. Santambrogio:
YoseUe: "trimming" Random Forest's training towards resource-constrained inference. 32-37 - Mehran Shoushtari Moghadam, Sercan Aygun, Mohsen Riahi Alam, M. Hassan Najafi:
P2LSG: Powers-of-2 Low-Discrepancy Sequence Generator for Stochastic Computing. 38-45 - Fangxin Liu, Haomin Li, Ning Yang, Yichi Chen, Zongwu Wang, Tao Yang, Li Jiang:
PAAP-HD: PIM-Assisted Approximation for Efficient Hyper-Dimensional Computing. 46-51 - Deyu Wang, Yuning Wang, Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner, Jiawei Xu, Li-Rong Zheng, Zhuo Zou:
FPGA-Based HPC for Associative Memory System. 52-57 - Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li:
Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. 58-64 - Bangqi Fu, Lixin Liu, Yang Sun, Wing Ho Lau, Martin D. F. Wong, Evangeline F. Y. Young:
CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs. 65-70 - Xingyu Tong, Zhijie Cai, Peng Zou, Min Wei, Yuan Wen, Zhifeng Lin, Jianli Chen:
O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs. 71-76 - Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang, Hao Wang, Yifan Li, Yihang Qiu, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang, Bei Yu, Biwei Xie, Yungang Bao:
iEDA: An Open-source infrastructure of EDA. 77-82 - Xingquan Li, Simin Tao, Shijian Chen, Zhisheng Zeng, Zhipeng Huang, Hongxi Wu, Weiguo Li, Zengrong Huang, Liwei Ni, Xueyan Zhao, He Liu, Shuaiying Long, Ruizhi Liu, Xiaoze Lin, Bo Yang, Fuxing Huang, Zonglin Yang, Yihang Qiu, Zheqing Shao, Jikang Liu, Yuyao Liang, Biwei Xie, Yungang Bao, Bei Yu:
iPD: An Open-source intelligent Physical Design Toolchain. 83-88 - Chedi Morchdi, Cheng-Hsiang Chiu, Yi Zhou, Tsung-Wei Huang:
A Resource-efficient Task Scheduling System using Reinforcement Learning : Invited Paper. 89-95 - Zhou Jin, Wenhao Li, Yinuo Bai, Tengcheng Wang, Yicheng Lu, Weifeng Liu:
Machine Learning and GPU Accelerated Sparse Linear Solvers for Transistor-Level Circuit Simulation: A Perspective Survey (Invited Paper). 96-101 - Zehua Yuan, Junhao Pan, Xiaofan Zhang, Deming Chen:
HomeSGN: A Smarter Home with Novel Rule Mining Enabled by a Scorer-Generator GAN. 102-108 - Zain Taufique, Antonio Miele, Pasi Liljeberg, Anil Kanduri:
Adaptive Workload Distribution for Accuracy-aware DNN Inference on Collaborative Edge Platforms. 109-114 - Minjoon Song, Faaiz Asim, Jongeun Lee:
Extending Neural Processing Unit and Compiler for Advanced Binarized Neural Networks. 115-120 - Ruhan Wang, Fahiz Baba-Yara, Fan Chen:
JustQ: Automated Deployment of Fair and Accurate Quantum Neural Networks. 121-126 - Daniel Schönberger, Stefan Hillmich, Matthias Brandl, Robert Wille:
Using Boolean Satisfiability for Exact Shuttling in Trapped-Ion Quantum Computers. 127-133 - Ryosuke Matsuo, Rudy Raymond, Shigeru Yamashita, Shin-ichi Minato:
Optimizing Decision Diagrams for Measurements of Quantum Circuits. 134-139 - Ching-Yao Huang, Wai-Kei Mak:
CTQr: Control and Timing-Aware Qubit Routing. 140-145 - Akul Malhotra, Chunguang Wang, Sumeet Kumar Gupta:
BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network Accelerators. 146-152 - Yiming Chen, Guodong Yin, Hongtao Zhong, Mingyen Lee, Huazhong Yang, Sumitha George, Vijaykrishnan Narayanan, Xueqing Li:
ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns. 153-158 - Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu:
A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators. 159-164 - Kunihiro Oshima, Kazunori Kuribara, Takashi Sato:
Design of Aging-Robust Clonable PUF Using an Insulator-Based ReRAM for Organic Circuits. 165-170 - Xu Cheng, Yuyang Ye, Guoqing He, Qianqian Song, Peng Cao:
Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction. 171-176 - Guoqing He, Wenjie Ding, Yuyang Ye, Xu Cheng, Qianqian Song, Peng Cao:
An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning. 177-182 - Hang Wu, Ning Xu, Wei W. Xing, Yuanqing Cheng:
BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization. 183-188 - Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif:
Timing Analysis beyond Complementary CMOS Logic Styles. 189-194 - Fan Jiang, Chengeng Li, Wei Zhang, Jiang Xu:
Collaborative Coalescing of Redundant Memory Access for GPU System. 195-200 - En-Ming Huang, Bo-Wun Cheng, Meng-Hsien Lin, Chun-Yi Lee, Tsung Tai Yeh:
WER: Maximizing Parallelism of Irregular Graph Applications Through GPU Warp EqualizeR. 201-206 - Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu:
SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design. 207-212 - Shuaibo Huang, Yuyang Ye, Hao Yan, Longxing Shi:
ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active Learning. 213-218 - Jackson Woodruff, Sam Ainsworth, Michael F. P. O'Boyle:
Secco: Codesign for Resource Sharing in Regular-Expression Accelerators. 219-224 - Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. 225-230 - Lei Dai, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li:
APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction. 231-237 - Meng Han, Liang Wang, Limin Xiao, Hao Zhang, Chenhao Zhang, Xilong Xie, Shuai Zheng, Jin Dong:
FuseFPS: Accelerating Farthest Point Sampling with Fusing KD-tree Construction for Point Clouds. 238-243 - Yashwant Moses, Madhav Rao:
A Fixed-Point Pre-Processing Hardware Architecture Design for Complex Independent Component Analysis. 244-249 - Xiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Hui Chen, Shiqing Li, Guochu Xiong, Weichen Liu:
Pearls Hide Behind Linearity: Simplifying Deep Convolutional Networks for Embedded Hardware Systems via Linearity Grafting. 250-255 - C. Harshitha, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran, Rajshekar Kalayappan:
On Decomposing Complex Test Cases for Efficient Post-silicon Validation. 256-261 - Guangyu Hu, Jianheng Tang, Changyuan Yu, Wei Zhang, Hongce Zhang:
DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction. 262-268 - Yufeng Li, Yiwei Ci, Qiusong Yang:
TIUP: Effective Processor Verification with Tautology-Induced Universal Properties. 269-274 - Christoph Hazott, Florian Stögmüller, Daniel Große:
Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing. 275-281 - Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. 282-287 - Tzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang:
An Effective Netlist Planning Approach for Double-sided Signal Routing. 288-293 - Min Wei, Xingyu Tong, Zhijie Cai, Peng Zou, Zhifeng Lin, Jianli Chen:
An Analytical Placement Algorithm with Routing topology Optimization. 294-299 - Yuan Wen, Benchao Zhu, Zhifeng Lin, Jianli Chen:
Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs. 300-305 - Ching-Yao Huang, Wai-Kei Mak:
Row Planning and Placement for Hybrid-Row-Height Designs. 306-311 - Chen-Hao Hsu, Xiaoqing Xu, Hao Chen, Dino Ruic, David Z. Pan:
TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design. 312-318 - Timothy Dunlap, Zelin Lu, Gang Qu:
Towards Finding the Sources of Polymorphism in Polymorphic Gates (Invited). 319-324 - Kotaro Matsuoka, Song Bian, Takashi Sato:
HOGE: Homomorphic Gate on An FPGA. 325-332 - Brian Udugama, Darshana Jayasinghe, Sri Parameswaran:
Sensors for Remote Power Attacks: New Developments and Challenges. 333-340 - Yun-Shan Hsieh, Bo-Jun Chen, Po-Chun Huang, Yuan-Hao Chang:
PRESS: Persistence Relaxation for Efficient and Secure Data Sanitization on Zoned Namespace Storage : (Invited Paper). 341-348 - Weimin Fu, Shijie Li, Yifang Zhao, Haocheng Ma, Raj Gautam Dutta, Xuan Zhang, Kaichen Yang, Yier Jin, Xiaolong Guo:
Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge. 349-354 - Nusrat Farzana Dipu, Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection. 355-361 - Zhuoran Li, Dan Zhao:
DeepIncept: Diversify Performance Counters with Deep Learning to Detect Malware. 362-367 - Sreenitha Kasarapu, Sanket Shukla, Sai Manoj Pudukotai Dinakarrao:
Resource- and Workload-aware Malware Detection through Distributed Computing in IoT Networks. 368-373 - Tao Zhang, Haoyu Yang, Kang Liu, Zhiyao Xie:
APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level. 374-379 - Yifei Zhou, Zijian Wang, Chao Wang:
E2E-Check: End to End GPU-Accelerated Design Rule Checking with Novel Mask Boolean Algorithms. 380-385 - Yanfang Liu, Wei W. Xing:
CIS: Conditional Importance Sampling for Yield Optimization of Analog and SRAM Circuits. 386-391 - Tianji Liu, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young:
FineMap: A Fine-grained GPU-parallel LUT Mapping Engine. 392-397 - Yukio Miyasaka:
Transduction Method for AIG Minimization. 398-403 - Gianluca Radi, Alessandro Tempia Calvino, Giovanni De Micheli:
In Medio Stat Virtus*: Combining Boolean and Pattern Matching. 404-410 - Hongjian Zhou, Yaguang Li, Xin Xiong, Pingqiang Zhou:
A Transferable GNN-based Multi-Corner Performance Variability Modeling for Analog ICs. 411-416 - Zhikai Wang, Jingbo Zhou, Xiaosen Liu, Yan Wang:
An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF Circuits. 417-422 - Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng:
MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier. 423-428 - Ruiyang Qin, Yuting Hu, Zheyu Yan, Jinjun Xiong, Ahmed Abbasi, Yiyu Shi:
FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models : (Invited Paper). 429-434 - Lily Jiaxin Wan, Yingbing Huang, Yuhong Li, Hanchen Ye, Jinghua Wang, Xiaofan Zhang, Deming Chen:
Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design Verification. 435-441 - Min Ye, Qiao Li, Daniel Wen, Tei-Wei Kuo, Chun Jason Xue:
wearMeter: an Accurate Wear Metric for NAND Flash Memory. 442-447 - Jingcheng Shen, Lang Yang, Linbo Long, Renping Liu, Zhenhua Tan, Congming Gao, Yi Jiang:
Overlapping Aware Zone Allocation for LSM Tree-Based Store on ZNS SSDs. 448-453 - Tom Glint, Manu Awasthi, Joycee Mekie:
Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data. 454-459 - Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. 460-465 - Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang:
Variational Label-Correlation Enhancement for Congestion Prediction. 466-471 - Tianliang Ma, Zhihui Deng, Xuguang Sun, Leilai Shao:
Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural Networks. 472-477 - Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar:
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. 478-483 - Hye Rim Ji, Jong Seong Kim, Jung Yun Choi, Jee Hyong Lee:
LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage. 484-490 - Hasini Witharana, Daniel Volya, Prabhat Mishra:
QcAssert: Quantum Device Testing with Concurrent Assertions. 491-496 - Shruti Pandey, Jayadeva, Smruti R. Sarangi:
HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector Generation. 497-502 - Zhiteng Chao, Xindi Zhang, Junying Huang, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li:
A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. 503-508 - Sina Bakhtavari Mamaghani, Priyanjana Pal, Mehdi Baradaran Tahoori:
A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures. 509-514 - Qiwei Dong, Xiaoru Xie, Zhongfeng Wang:
SWAT: An Efficient Swin Transformer Accelerator Based on FPGA. 515-520 - Hongji Wang, Yueyin Bai, Jun Yu, Kun Wang:
TransFRU: Efficient Deployment of Transformers on FPGA with Full Resource Utilization. 521-526 - Zihang Ma, Zeyu Li, Yuanfang Wang, Yu Li, Jun Yu, Kun Wang:
Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier. 527-532 - Jinho Yang, Sungwoong Yune, Sukbin Lim, Donghyuk Kim, Joo-Young Kim:
ACane: An Efficient FPGA-based Embedded Vision Platform with Accumulation-as-Convolution Packing for Autonomous Mobile Robots. 533-538 - Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka:
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. 539-544 - Cheng-Yang Chang, Chi-Tse Huang, Yu-Chuan Chuang, Kuang-Chao Chou, An-Yeu Andy Wu:
BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based Accelerator. 545-550 - Lizhou Wu, Chenyang Zhao, Jingbo Wang, Xueru Yu, Shoumian Chen, Chen Li, Jun Han, Xiaoyong Xue, Xiaoyang Zeng:
A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. 551-556 - Yue Pan, Minxuan Zhou, Chonghan Lee, Zheyu Li, Rishika Kushwah, Vijaykrishnan Narayanan, Tajana Rosing:
PRIMATE: Processing in Memory Acceleration for Dynamic Token-pruning Transformers. 557-563 - Huayang Cai, Genggeng Liu, Wenzhong Guo, Zipeng Li, Tsung-Yi Ho, Xing Huang:
Adaptive Control-Logic Routing for Fully Programmable Valve Array Biochips Using Deep Reinforcement Learning. 564-569 - Genggeng Liu, Yuqin Zeng, Yuhan Zhu, Huayang Cai, Wenzhong Guo, Zipeng Li, Tsung-Yi Ho, Xing Huang:
Towards Automated Testing of Multiplexers in Fully Programmable Valve Array Biochips. 570-575 - Jan Drewniok, Marcel Walter, Robert Wille:
The Need for Speed: Efficient Exact Simulation of Silicon Dangling Bond Logic. 576-581 - Rassul Bairamkulov, Giovanni De Micheli:
Towards Multiphase Clocking in Single-Flux Quantum Systems. 582-587 - Alessandro Tempia Calvino, Giovanni De Micheli:
Algebraic and Boolean Methods for SFQ Superconducting Circuits. 588-593 - Pei-Pei Chen, Xiang-Min Yang, Yu-Cheng He, Yung-Chih Chen, Yi-Ting Li, Chun-Yao Wang:
LOOPLock 3.0: A Robust Cyclic Logic Locking Approach. 594-599 - Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto:
Logic Locking over TFHE for Securing User Data and Algorithms. 600-605 - Yeganeh Aghamohammadi, Amin Rezaei:
LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-based Oracle-Less Attack on Logic Locking. 606-611 - Brojogopal Sapui, Mehdi B. Tahoori:
Power Side-Channel Analysis and Mitigation for Neural Network Accelerators based on Memristive Crossbars. 612-617 - Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi:
Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits. 618-624 - Xiao Dong, Songyu Sun, Yangfan Jiang, Jingtong Hu, Dawei Gao, Cheng Zhuo:
SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation. 625-630 - Jiawen Cheng, Zhiqiang Liu, Lingjie Li, Wenjian Yu:
Nested Dissection Based Parallel Transient Power Grid Analysis on Public Cloud Virtual Machines. 631-637 - Kexin Zhu, Runjie Zhang, Qing He:
Efficient Sublogic-Cone-Based Switching Activity Estimation using Correlation Factor. 638-643 - Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan:
ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning. 644-650 - Dinghao Chen, Wenjie Zhu, Xiaoman Yang, Pengpeng Ren, Zhigang Ji, Hai-Bao Chen:
Physics-Informed Learning for EPG-Based TDDB Assessment. 651-656 - Supriyo Maji, Ahmet Faruk Budak, Souradip Poddar, David Z. Pan:
Toward End-to-End Analog Design Automation with ML and Data-Driven Approaches (Invited Paper). 657-664 - Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar:
Reinforcing the Connection between Analog Design and EDA (Invited Paper). 665-670 - Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). 671-678 - Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu, Keren Zhu:
Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper). 679-685 - Niko Zurstraßen, Ruben Brandhofer, José Cubero-Cascante, Nils Bosbach, Lukas Jünger, Rainer Leupers:
The Optimal Quantum of Temporal Decoupling. 686-691 - Lucas Klemmer
, Daniel Große:
Towards a Highly Interactive Design-Debug-Verification Cycle. 692-697 - Hsuan-Yi Lin, Ren-Song Tsay:
Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance Estimation. 698-703 - Saehanseul Yi, Nikil D. Dutt:
BoostIID: Fault-agnostic Online Detection of WCET Changes in Autonomous Driving. 704-709 - Ivannia Gomez Moreno, Xiaofan Yu, Tajana Rosing:
KalmanHD: Robust On-Device Time Series Forecasting with Hyperdimensional Computing. 710-715 - Haomin Li, Fangxin Liu, Yichi Chen, Li Jiang:
HyperFeel: An Efficient Federated Learning Framework Using Hyperdimensional Computing. 716-721 - Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie:
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. 722-727 - Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, Bei Yu:
LSTP: A Logic Synthesis Timing Predictor. 728-733 - Alex Chan, Danil Sokolov, Victor Khomenko, Alex Yakovlev:
Bridging the Design Methodologies of Burst-Mode Specifications and Signal Transition Graphs. 734-739 - Anurup Saha, Chandramouli N. Amarnath, Kwondo Ma, Abhijit Chatterjee:
Signature Driven Post-Manufacture Testing and Tuning of RRAM Spiking Neural Networks for Yield Recovery. 740-745 - Tianshu Hou, Yuan Ren, Wenyong Zhou, Can Li, Zhongrui Wang, Hai-Bao Chen, Ngai Wong:
Physics-Informed Learning for Versatile RRAM Reset and Retention Simulation. 746-751 - Surendra Hemaram, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Gouri Sankar Kar:
Hard Error Correction in STT-MRAM. 752-757 - Zhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Yaotian Liu, Jae-Sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Jeff Zhang, Yu Cao:
Exploiting 2.5D/3D Heterogeneous Integration for AI Computing. 758-764 - Zhuoping Yang, Shixin Ji, Xingzhen Chen, Jinming Zhuang, Weifeng Zhang, Dharmesh Jani, Peipei Zhou:
Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets. 765-770 - Ankur Limaye, Claudio Barone, Nicolas Bohm Agostini, Marco Minutoli, Joseph B. Manzano, Vito Giovanni Castellana, Giovanni Gozzi, Michele Fiorito, Serena Curzel, Fabrizio Ferrandi, Antonino Tumeo:
Towards Automated Generation of Chiplet-Based Systems Invited Paper. 771-776 - Robert Khasanov, Marc Dietrich, Jerónimo Castrillón:
Flexible Spatio-Temporal Energy-Efficient Runtime Management. 777-784 - Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow. 785-791 - Matthias Becker:
Meeting Job-Level Dependencies by Task Merging. 792-798 - Xuchen Gao, Yunhui Qiu, Yuan Dai, Wenbo Yin, Lingli Wang:
A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated Operators. 799-804 - Yihong Hu, Nuo Xu, Chaochao Feng, Wei Tong, Kang Liu, Liang Fang:
LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing. 805-811 - Sven Thijssen, Muhammad Rashedul Haq Rashed, Hao Zheng, Sumit Kumar Jha, Rickard Ewetz:
Towards Area-Efficient Path-Based In-Memory Computing using Graph Isomorphisms. 812-817 - Sven Thijssen, Muhammad Rashedul Haq Rashed, Sumit Kumar Jha, Rickard Ewetz:
READ-based In-Memory Computing using Sentential Decision Diagrams. 818-823 - Liang Zhao, Yu Qian, Fanzi Meng, Xiapeng Xu, Xunzhao Yin, Cheng Zhuo:
ConvFIFO: A Crossbar Memory PIM Architecture for ConvNets Featuring First-In-First-Out Dataflow. 824-829 - Ruokai Yin, Yuhang Li, Abhishek Moitra, Priyadarshini Panda:
MINT: Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks. 830-835 - Yuxuan Yang, Zihao Xuan, Yi Kang:
TQ-TTFS: High-Accuracy and Energy-Efficient Spiking Neural Networks Using Temporal Quantization Time-to-First-Spike Neuron. 836-841 - Fangxin Liu, Haomin Li, Ning Yang, Zongwu Wang, Tao Yang, Li Jiang:
TEAS: Exploiting Spiking Activity for Temporal-wise Adaptive Spiking Neural Networks. 842-847 - Zhenhang Zhang, Jingang Jin, Haowen Fang, Qinru Qiu:
SOLSA: Neuromorphic Spatiotemporal Online Learning for Synaptic Adaptation. 848-853 - Raphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jiménez, Mauricio Gomes de Queiroz, Benoît Charbonnier, Fabio Pavanello, Ian O'Connor, Sébastien Le Beux:
Signed Convolution in Photonics with Phase-Change Materials using Mixed-Polarity Bitstreams. 854-859 - Yihao Liu, Yaoyao Ye:
An Efficient Branch-and-Bound Routing Algorithm for Optical NoCs. 860-865 - Baiyu Chen, Zhiqiang Liu, Yibin Zhang, Wenjian Yu:
Boosting Graph Spectral Sparsification via Parallel Sparse Approximate Inverse of Cholesky Factor. 866-871 - Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, Xuan Zeng:
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. 872-877 - Jiasong Chen, Zeming Xie, Weipeng Liang, Bosheng Liu, Xin Zheng, Jigang Wu, Xiaoming Xiong:
Quantization-aware Optimization Approach for CNNs Inference on CPUs. 878-883 - Shiyuan Huang, Fangxin Liu, Tian Li, Zongwu Wang, Haomin Li, Li Jiang:
TSTC: Enabling Efficient Training via Structured Sparse Tensor Compilation. 884-889 - Caleb Tung, Nicholas Eliopoulos, Purvish Jajal, Gowri Ramshankar, Cheng-Yun Yang, Nicholas Synovic, Xuecen Zhang, Vipin Chaudhary, George K. Thiruvathukal, Yung-Hsiang Lu:
An automated approach for improving the inference latency and energy efficiency of pretrained CNNs by removing irrelevant pixels with focused convolutions. 890-895 - Fatemeh Asgarinejad, Justin Morris, Tajana Rosing, Baris Aksanli:
PIONEER: Highly Efficient and Accurate Hyperdimensional Computing using Learned Projection. 896-901 - Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li:
Logic Design of Neural Networks for High-Throughput and Low-Power Applications. 902-907 - Yi Li, Aarti Gupta, Sharad Malik:
Exact Scheduling to Minimize Off-Chip Data Movement for Deep Learning Accelerators. 908-914 - Priscilla Sharon Allwin, Manil Dev Gomony, Marc Geilen:
Run-time Non-uniform Quantization for Dynamic Neural Networks in Wireless Communication. 915-920 - Xilang Zhou, Shuyang Li, Haodong Lu, Kun Wang:
PipeFuser: Building Flexible Pipeline Architecture for DNN Accelerators via Layer Fusion. 921-926 - Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang:
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. 927-932 - Zhaoxiang Liu, Kejun Chen, Dean Sullivan, Orlando Arias, Raj Dutta, Yier Jin, Xiaolong Guo:
Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware Perspective. 933-938 - Garett Cunningham, Harsha Chenji, David Juedes, Avinash Karanth:
d-GUARD: Thwarting Denial-of-Service Attacks via Hardware Monitoring of Information Flow using Language Semantics in Embedded Systems. 939-944 - Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler:
Security Coverage Metrics for Information Flow at the System Level. 945-950 - Wei-Kai Liu, Benjamin Tan, Jason M. Fung, Krishnendu Chakrabarty:
Theoretical Patchability Quantification for IP-Level Hardware Patching Designs. 951-956 - Levent Aksoy, Debapriya Basu Roy, Malik Imran, Samuel Pagliarini:
Multiplierless Design of High-Speed Very Large Constant Multiplications. 957-962 - Ping Zhang, Pengju Yao, Xingquan Li, Bei Yu, Wenxing Zhu:
V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting. 963-968 - Yun-Kai Fang, Ye-Chih Lin, Ting-Chi Wang:
A Fast and Robust Global Router with Capacity Reduction Techniques. 969-974 - Zhongdong Qi, Shizhe Hu, Qi Peng, Hailong You, Chao Han, Zhangming Zhu:
A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides. 975-980
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