default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDChun-Yao Wang
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j35]Yu-Chuan Yen
, Meng-Jing Li, Yi-Ting Li, Yung-Chih Chen, Ihao Chen, Chun-Yao Wang:
9-Input Threshold Function Identification Using a New Necessary Condition of Threshold Function. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4676-4686 (2024)- [c76]Pei-Pei Chen, Xiang-Min Yang, Yu-Cheng He, Yung-Chih Chen, Yi-Ting Li, Chun-Yao Wang:
LOOPLock 3.0: A Robust Cyclic Logic Locking Approach. ASPDAC 2024: 594-599 - [c75]Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang:
A Hybrid Approach to Reverse Engineering on Combinational Circuits. DATE 2024: 1-2 - [c74]Yong-Fong Chang, Yung-Chih Chen, Yu-Chen Cheng, Shu-Hong Lin, Che-Hsu Lin, Chun-Yuan Chen, Yu-Hsuan Chen, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Shih-Chieh Chang, Yi-Ting Li, Chun-Yao Wang:
IR drop Prediction Based on Machine Learning and Pattern Reduction. ACM Great Lakes Symposium on VLSI 2024: 516-519 - [c73]Wuqian Tang, Chuan-Shun Huang, Yung-Chih Chen, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang:
Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method. SOCC 2024: 1-6 - 2023
- [j34]Meng-Jing Li, Yu-Chuan Yen, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Constructive Approach for Threshold Function Identification. ACM Trans. Design Autom. Electr. Syst. 28(5): 86:1-86:19 (2023) - [c72]Chun-Ting Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee. ASP-DAC 2023: 146-151 - [c71]Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli. ASP-DAC 2023: 696-701 - [c70]Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, Tsung-Wei Huang:
Invited Paper: Overview of 2023 CAD Contest at ICCAD. ICCAD 2023: 1-6 - [c69]Hsin-Ping Yen, Shiuan-Hau Huang, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation. ISQED 2023: 1-8 - 2022
- [j33]Xiang-Min Yang, Pei-Pei Chen, Hsiao-Yu Chiang, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 29-34 (2022) - [j32]Chang-Cheng Ko, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
Majority Logic Circuit Minimization Using Node Addition and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 642-655 (2022) - [j31]Chia-Chun Lin, Ciao-Syun Lin, You-Hsuen Tsai, Yung-Chih Chen, Chun-Yao Wang:
Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1412-1422 (2022) - [j30]Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4821-4825 (2022) - [c68]Yu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato:
Overview of 2022 CAD Contest at ICCAD. ICCAD 2022: 92:1-92:3 - [c67]Pei-Pei Chen, Xiang-Min Yang, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0. ICCAD 2022: 155:1-155:7 - 2021
- [j29]Chun-Yao Wang, Ying-Jen Chen, Chen-Fu Chien:
Industry 3.5 to empower smart production for poultry farming and an empirical study for broiler live weight prediction. Comput. Ind. Eng. 151: 106931 (2021) - [j28]Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, Chun-Yao Wang:
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. ACM J. Emerg. Technol. Comput. Syst. 17(2): 15:1-15:23 (2021) - [c66]Chia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-Pei Chen, Yung-Chih Chen, Chun-Yao Wang:
A General Equivalence Checking Framework for Multivalued Logic. ASP-DAC 2021: 61-66 - [c65]Kit Seng Tam, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
An Efficient Approximate Node Merging with an Error Rate Guarantee. ASP-DAC 2021: 266-271 - [c64]Tsung-Wei Huang, Yu-Guang Chen, Chun-Yao Wang, Takashi Sato:
Overview of 2021 CAD Contest at ICCAD. ICCAD 2021: 1-3 - [c63]Hsin-Tsung Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays. ISQED 2021: 316 - [c62]Wen-Chih Hsu, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
On Reduction of Computations for Threshold Function Identification. SoCC 2021: 146-151 - [c61]Yi-Ting Lin, Chun-Jui Chen, Pei-Yi Kuo, Si-Huei Lee, Chia-Chun Lin, Yun-Ju Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
An IMU-aided Fitness System. SoCC 2021: 224-229 - [c60]Shiuan-Hau Huang, Hsin-Ping Yen, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
Cluster Tool Performance Analysis using Graph Database. SoCC 2021: 230-235 - 2020
- [j27]Hsiao-Yu Chiang, Yung-Chih Chen, De-Xuan Ji, Xiang-Min Yang, Chia-Chun Lin, Chun-Yao Wang:
LOOPLock: Logic Optimization-Based Cyclic Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2178-2191 (2020) - [j26]Chia-Chun Lin, Chin-Heng Liu, Yung-Chih Chen, Chun-Yao Wang:
A New Necessary Condition for Threshold Function Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5304-5308 (2020) - [c59]Ya-Chun Chang, Chia-Chun Lin, Yi-Ting Lin, Yung-Chih Chen, Chun-Yao Wang:
A Convolutional Result Sharing Approach for Binarized Neural Network Inference. DATE 2020: 780-785 - [c58]Teng-Chia Wang, Yan-Ping Chang, Chun-Jui Chen, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement. ISQED 2020: 173-178 - [c57]Chun-Jui Chen, Yi-Ting Lin, Chia-Chun Lin, Yung-Chih Chen, Yun-Ju Lee, Chun-Yao Wang:
Rehabilitation System for Limbs using IMUs. ISQED 2020: 285-291 - [c56]Chia-Chun Lin, Kit Seng Tam, Chana-Cheng Ko, Hsin-Ping Yen, Shenz-Hsiu Wei, Yung-Chih Chen, Chun-Yao Wang:
A Dynamic Expansion Order Algorithm for the SAT-based Minimization. SoCC 2020: 271-276
2010 – 2019
- 2019
- [j25]Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, Shigeru Yamashita:
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2284-2297 (2019) - [c55]De-Xuan Ji, Hsiao-Yu Chiang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
A Glitch Key-Gate for Logic Locking. SoCC 2019: 74-79 - [c54]Yan-Ping Chang, Teng-Chia Wang, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises. SoCC 2019: 197-202 - 2018
- [j24]Hsin-Pei Wang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2842-2852 (2018) - [c53]Tung-Yuan Lee, Chia-Cheng Wu, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
Logic optimization with considering boolean relations. DATE 2018: 761-766 - [c52]Yung-An Lai, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. DATE 2018: 773-778 - [c51]Chia-Cheng Wu, Tung-Yuan Lee, Yung-An Lai, Hsin-Pei Wang, De-Xuan Ji, Yan-Ping Chang, Teng-Chia Wang, Chin-Heng Liu, Chun-Yao Wang, Yung-Chih Chen:
A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification. ACM Great Lakes Symposium on VLSI 2018: 447-450 - [c50]Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang:
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. ISVLSI 2018: 257-262 - [c49]Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang:
Using range-equivalent circuits for facilitating bounded sequential equivalence checking. VLSI-DAT 2018: 1-4 - 2017
- [j23]Ying-Chin Lin, Chun-Yao Wang, Jing-Yun Zeng:
A case study on mathematical expression recognition to GPU. J. Supercomput. 73(8): 3333-3343 (2017) - [j22]Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan:
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1477-1489 (2017) - [c48]Chun-Che Chung, Yung-Chih Chen, Chun-Yao Wang, Chia-Cheng Wu:
Majority logic circuits optimisation by node merging. ASP-DAC 2017: 714-719 - [c47]Chia-Chun Lin, Chiao-Wei Huang, Chun-Yao Wang, Yung-Chih Chen:
In&Out: Restructuring for threshold logic network optimization. ISQED 2017: 413-418 - 2016
- [j21]Tai-Lin Chen, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm. J. Multiple Valued Log. Soft Comput. 27(1): 1-19 (2016) - [j20]Chen-Yu Lin, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Chiou-Ting Hsu:
Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks. IEEE Trans. Multi Scale Comput. Syst. 2(4): 225-233 (2016) - [j19]Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta, Vijaykrishnan Narayanan:
Area-Aware Decomposition for Single-Electron Transistor Arrays. ACM Trans. Design Autom. Electr. Syst. 21(4): 70:1-70:20 (2016) - [j18]Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2321-2334 (2016) - [c46]Yu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang:
MajorSat: A SAT solver to majority logic. ASP-DAC 2016: 480-485 - 2015
- [j17]Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen:
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 615-628 (2015) - [j16]Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan:
Synthesis for Width Minimization in the Single-Electron Transistor Array. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2862-2875 (2015) - [c45]Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. ASP-DAC 2015: 118-123 - [c44]Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang:
Using structural relations for checking combinationality of cyclic circuits. DATE 2015: 325-328 - [c43]Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen:
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. ICCD 2015: 236-243 - [c42]Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, Chun-Yao Wang:
Synthesis and verification of cyclic combinational circuits. SoCC 2015: 257-262 - 2014
- [j15]Yu-Liang Hsu, Pau-Choo Chung, Wei-Hsin Wang, Ming-Chyi Pai, Chun-Yao Wang, Chien-Wen Lin, Hao-Li Wu, Jeen-Shing Wang:
Gait and Balance Analysis for Patients With Alzheimer's Disease Using an Inertial-Sensor-Based Wearable Instrument. IEEE J. Biomed. Health Informatics 18(6): 1822-1830 (2014) - [c41]Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang:
Rewiring for threshold logic circuit minimization. DATE 2014: 1-6 - [c40]Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
Width minimization in the Single-Electron Transistor array synthesis. DATE 2014: 1-4 - [c39]Zheng Zhao, Chian-Wei Liu, Chun-Yao Wang, Weikang Qian:
BDD-based synthesis of reconfigurable single-electron transistor arrays. ICCAD 2014: 47-54 - [c38]Wei-Hsin Wang, Yu-Liang Hsu, Ming-Chyi Pai, Cheng-Hsiung Wang, Chun-Yao Wang, Chien-Wen Lin, Hao-Li Wu, Pau-Choo Chung:
Alzheimer's disease classification based on gait information. IJCNN 2014: 3251-3257 - 2013
- [j14]Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan:
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. ACM J. Emerg. Technol. Comput. Syst. 9(1): 5:1-5:20 (2013) - [j13]Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang:
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1473-1483 (2013) - [c37]Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
On reconfigurable single-electron transistor arrays synthesis using reordering techniques. DATE 2013: 1807-1812 - [c36]Chen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
Sensitization criterion for threshold logic circuits and its application. ICCAD 2013: 226-233 - [c35]Yen-Chi Yang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
Pattern generation for Mutation Analysis using Genetic Algorithms. ISCAS 2013: 2545-2548 - 2012
- [j12]Daniel J. Buehrer, Chun-Yao Wang:
Deco: A Decentralized, Cooperative Atomic Commit Protocol. J. Comput. Networks Commun. 2012: 782517:1-782517:14 (2012) - [j11]Yung-Chih Chen, Chun-Yao Wang:
Logic Restructuring Using Node Addition and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 260-270 (2012) - [c34]Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen:
A probabilistic analysis method for functional qualification under Mutation Analysis. DATE 2012: 147-152 - [c33]Daniel J. Buehrer, Chun-Yao Wang:
CA-ABAC: Class Algebra Attribute-Based Access Control. Web Intelligence/IAT Workshops 2012: 220-225 - [c32]Pau-Choo Chung, Yu-Liang Hsu, Chun-Yao Wang, Chien-Wen Lin, Jeen-Shing Wang, Ming-Chyi Pai:
Gait analysis for patients with Alzheimer'S disease using a triaxial accelerometer. ISCAS 2012: 1323-1326 - [c31]Ching-Yi Huang, Daw-Ming Lee, Chun-Chi Lin, Chun-Yao Wang:
Error Injection & Correction: An efficient formal logic restructuring algorithm. ISOCC 2012: 188-191 - 2011
- [c30]Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan:
Automated mapping for reconfigurable single-electron transistor arrays. DAC 2011: 878-883 - [c29]Pin-Yi Kuo, Chun-Yao Wang, Ching-Yi Huang:
On rewiring and simplification for canonicity in threshold logic circuits. ICCAD 2011: 396-403 - [c28]Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin:
A register-transfer level testability analyzer. SoCC 2011: 219-224 - 2010
- [j10]Yung-Chih Chen, Chun-Yao Wang:
Fast Node Merging With Don't Cares Using Logic Implications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1827-1832 (2010) - [c27]Yung-Chih Chen, Chun-Yao Wang:
Node addition and removal in the presence of don't cares. DAC 2010: 505-510 - [c26]Daniel J. Buehrer, Chun-Yao Wang:
Distributed Transactions for Semantic Web Workflows - Overcoming the CAP Limitations on Virtual Organizations. ISPA 2010: 465-469 - [c25]Daniel J. Buehrer, Chun-Yao Wang, Li-Ren Chien:
The Cadabia Cloud. ISPA 2010: 631-638
2000 – 2009
- 2009
- [j9]Chen-Hsuan Lin, Chun-Yao Wang, Yung-Chih Chen:
Dependent-Latch Identification in Reachable State Space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1113-1126 (2009) - [c24]Chen-Hsuan Lin, Chun-Yao Wang:
Dependent latch identification in the reachable state space. ASP-DAC 2009: 630-635 - [c23]Chun-Chi Lin, Chun-Yao Wang:
Rewiring using IRredundancy Removal and Addition. DATE 2009: 324-327 - [c22]Yung-Chih Chen, Chun-Yao Wang:
Enhancing SAT-based sequential depth computation by pruning search space. ACM Great Lakes Symposium on VLSI 2009: 397-400 - [c21]Yung-Chih Chen, Chun-Yao Wang:
Fast detection of node mergers using logic implications. ICCAD 2009: 785-788 - [c20]Meng-Syue Chan, Chun-Yao Wang, Yung-Chih Chen:
An efficient approach to sip design integration. ISQED 2009: 241-247 - [c19]Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang:
A novel ACO-based pattern generation for peak power estimation in VLSI circuits. ISQED 2009: 317-323 - 2008
- [j8]Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou:
Verification of Pin-Accurate Port Connections. IEEE Des. Test Comput. 25(5): 478-486 (2008) - [j7]Min-Lun Chuang, Chun-Yao Wang:
Synthesis of reversible sequential elements. ACM J. Emerg. Technol. Comput. Syst. 3(4): 4:1-4:19 (2008) - [j6]Yung-Chih Chen, Chun-Yao Wang:
An Implicit Approach to Minimizing Range-Equivalent Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1942-1955 (2008) - [j5]Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen:
Novel Probabilistic Combinational Equivalence Checking. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 365-375 (2008) - [c18]Chun-Yao Wang, Daniel J. Buehrer:
A Ring-Based Decentralized Collaborative Non-blocking Atomic Commit Protocol. IAT 2008: 395-398 - [c17]Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen:
A Statistic-Based Approach to Testability Analysis. ISQED 2008: 267-270 - 2007
- [j4]Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang:
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2222-2227 (2007) - [c16]Min-Lun Chuang, Chun-Yao Wang:
Synthesis of Reversible Sequential Elements. ASP-DAC 2007: 420-425 - [c15]Tsung-Lin Lee, Chun-Yao Wang:
Recognition of Fanout-free Functions. ASP-DAC 2007: 426-431 - [c14]Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho:
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. ISQED 2007: 344-349 - 2006
- [c13]Ming-Hong Su, Chun-Yao Wang:
High level equivalence symmetric input identification. ASP-DAC 2006: 249-253 - [c12]Shih-Chieh Wu, Chun-Yao Wang, Jan-an Hsieh:
The Potential and Limitation of Probability-Based Combinational Equivalence Checking. ATS 2006: 103-108 - [c11]Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen:
Language-Based High Level Transaction Extraction on On-chip Buses. ISQED 2006: 231-236 - [c10]Shih-Chieh Wu, Chun-Yao Wang:
PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking. VLSI-SoC 2006: 104-109 - 2005
- [c9]Yung-Chih Chen, Chun-Yao Wang:
An Improved Approach for AlternativeWires Identi.cation. ICCD 2005: 711-716 - 2004
- [c8]Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou:
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. ICCD 2004: 417-419 - [c7]Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang:
Verification on Port Connections. ITC 2004: 830-836 - [c6]Daniel J. Buehrer, Chun-Yao Wang:
Using a Class Algebra Ontology To Define Conversions between OWL/SQL/Java Beans. Web Intelligence 2004: 752-754 - 2003
- [j3]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
Automatic interconnection rectification for SoC design verification based on the port order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 104-114 (2003) - [c5]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An automatic interconnection rectification technique for SoC design integration. ASP-DAC 2003: 108-111 - [c4]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
SoC design integration by using automatic interconnection rectification. ISCAS (4) 2003: 744-747 - 2002
- [j2]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
On automatic-verification pattern generation for SoC withport-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 466-479 (2002) - [j1]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1225-1232 (2002) - 2001
- [c3]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. Asian Test Symposium 2001: 431-436 - [c2]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. HLDVT 2001: 145-150 - [c1]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An AVPG for SOC design verification with port order fault model. ISCAS (5) 2001: 259-262
Coauthor Index
[j35] [c76] [c75] [c74] [c73] [j34] [c72] [c71] [c69] [j33] [j32] [j31] [j30] [c67] [j28] [c66] [c65] [c63] [c62] [c61] [c60] [j27] [j26] [c59] [c58] [c57] [c56] [j25] [c55] [c54] [j24] [c53] [c52] [c51] [c49] [j22] [c48] [c47] [j21] [j20] [j19] [j18] [c46] [j17] [j16] [c45] [c44] [c42] [c41] [c40] [j14] [j13] [c37] [c36] [c35] [j11] [c34] [c30] [j10] [c27] [j9] [c22] [c21] [c20] [c19] [j6] [j5] [c17] [c11] [c9]
Narayanan Vijaykrishnan
aka: Vijaykrishnan Narayanan
aka: Vijaykrishnan Narayanan
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-01-21 00:21 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
