"Majority Logic Circuit Minimization Using Node Addition and Removal."

Chang-Cheng Ko et al. (2022)

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DOI: 10.1109/TCAD.2021.3060648

access: closed

type: Journal Article

metadata version: 2022-03-15

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Chang-Cheng Ko, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
Majority Logic Circuit Minimization Using Node Addition and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 642-655 (2022)

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