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Soumya Eachempati
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2010 – 2019
- 2013
- [j3]Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan:
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. ACM J. Emerg. Technol. Comput. Syst. 9(1): 5:1-5:20 (2013) - 2011
- [j2]Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das:
RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. 71(5): 625-640 (2011) - [c9]Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan:
Automated mapping for reconfigurable single-electron transistor arrays. DAC 2011: 878-883 - 2010
- [c8]Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan:
Optimizing power and performance for reliable on-chip networks. ASP-DAC 2010: 431-436
2000 – 2009
- 2009
- [j1]Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud:
Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect. IET Circuits Devices Syst. 3(2): 64-75 (2009) - [c7]Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das:
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA 2009: 175-186 - [c6]Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das:
A case for dynamic frequency tuning in on-chip networks. MICRO 2009: 292-303 - [c5]Yuan Xie, Soumya Eachempati, Aditya Yanamandra, Vijaykrishnan Narayanan, Mary Jane Irwin:
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network. NANOARCH 2009: 51-56 - 2008
- [c4]Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das:
MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA 2008: 251-261 - [c3]Soumya Eachempati, Vinay Saripalli, Narayanan Vijaykrishnan, Suman Datta:
Reconfigurable BDD based quantum circuits. NANOARCH 2008: 61-67 - 2007
- [c2]Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud:
Assessing carbon nanotube bundle interconnect for future FPGA architectures. DATE 2007: 307-312 - [c1]Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud:
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. ISVLSI 2007: 516-517
Coauthor Index
aka: Vijaykrishnan Narayanan
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