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ORCIDShing-Wu Tung
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2010 – 2019
- 2013
[c13]Wei-Xiang Tang, Shui-An Wen, Shing-Wu Tung, Keng-Yu Lin, Chun-Chih Chen, Ching-Lung Su:
A 42.5µW/MHz ultra-low power 32-bit microcontroller - SPARK. ICICS 2013: 1-4- [c12]Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai:
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. VLSI-DAT 2013: 1-4 - 2012
- [c11]Po-Han Huang, Chi-Hung Lin, Hsien-Ching Hsieh, Huang-Lun Lin, Shing-Wu Tung:
Low power and high performance 3-D multimedia platform. Hot Chips Symposium 2012: 1-3 - [c10]Shui-An Wen, Chun-Chin Chen, Shing-Wu Tung:
A power management technology for mobile embedded system. VLSI-DAT 2012: 1-4 - 2011
- [c9]Jen-Chieh Yeh, Kung-Ming Ji, Shing-Wu Tung, Shau-Yin Tseng:
Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology. HPCC 2011: 851-856 - [c8]Hsien-Ching Hsieh, Shui-An Wen, Che-Yu Liao, Huang-Lun Lin, Po-Han Huang, Shing-Wu Tung:
Low power design and dynamic power management system for VLIW DSP subsystem. ISPACS 2011: 1-5
2000 – 2009
- 2003
- [j4]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
Automatic interconnection rectification for SoC design verification based on the port order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 104-114 (2003) - [c7]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An automatic interconnection rectification technique for SoC design integration. ASP-DAC 2003: 108-111 - [c6]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
SoC design integration by using automatic interconnection rectification. ISCAS (4) 2003: 744-747 - 2002
- [j3]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
On automatic-verification pattern generation for SoC withport-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 466-479 (2002) - [j2]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1225-1232 (2002) - 2001
- [c5]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. Asian Test Symposium 2001: 431-436 - [c4]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. HLDVT 2001: 145-150 - [c3]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An AVPG for SOC design verification with port order fault model. ISCAS (5) 2001: 259-262 - [c2]Chih-Yuan Chen, Shing-Wu Tung:
ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. ISQED 2001: 405-408
1990 – 1999
- 1998
- [j1]Shing-Wu Tung, Jing-Yang Jou:
A Logical Fault Model for Library Coherence Checking. J. Inf. Sci. Eng. 14(3): 567-586 (1998) - [c1]Shing-Wu Tung, Jing-Yang Jou:
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. Asian Test Symposium 1998: 402-407
Coauthor Index
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