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ORCIDICCAD 2021: Munich, Germany
- IEEE/ACM International Conference On Computer Aided Design, ICCAD 2021, Munich, Germany, November 1-4, 2021. IEEE 2021, ISBN 978-1-6654-4507-8
- Kangkyu Park, Yunki Han, Lee-Sup Kim:
Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation Sparsity. 1-9 - Jilan Lin, Shuangchen Li, Yufei Ding, Yuan Xie:
Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications. 1-9 - Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim:
Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. 1-9 - Tsun-Ming Tseng
, Meng Lian, Mengchu Li, Philipp Rinklin, Leroy Grob, Bernhard Wolfrum, Ulf Schlichtmann:
Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed Electronics. 1-8 - Andreas Krinke, Shubham Rai, Akash Kumar, Jens Lienig:
Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies. 1-9 - Daniel Manu, Yi Sheng, Junhuan Yang, Jieren Deng, Tong Geng, Ang Li, Caiwen Ding, Weiwen Jiang, Lei Yang:
FL-DISCO: Federated Generative Adversarial Network for Graph-based Molecule Drug Discovery: Special Session Paper. 1-7 - Jai-Ming Lin, Wei-Fan Huang, Yao-Chieh Chen, Yi-Ting Wang, Po-Wen Wang:
DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs. 1-8 - Mengquan Li, Zhongzhi Yu, Yongan Zhang, Yonggan Fu, Yingyan Lin:
O-HAS: Optical Hardware Accelerator Search for Boosting Both Acceleration Performance and Development Speed. 1-9 - Dewen Zeng, John N. Kheir, Peng Zeng, Yiyu Shi:
Contrastive Learning with Temporal Correlated Medical Images: A Case Study using Lung Segmentation in Chest X-Rays (Invited Paper). 1-7 - Xiaoxuan Yang, Syrine Belakaria, Biresh Kumar Joardar, Huanrui Yang, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty, Hai Helen Li:
Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise. 1-9 - Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen:
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. 1-9 - Amur Ghose, Vincent Zhang, Yingxue Zhang, Dong Li, Wulong Liu, Mark Coates:
Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction. 1-9 - Jens Lienig, Susann Rothe, Matthias Thiele, Nikhil Rangarajan, Mohammed Ashraf, Mohammed Nabeel, Hussam Amrouch, Ozgur Sinanoglu, Johann Knechtel:
Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper. 1-9 - Sumit K. Mandal, Jie Tong, Raid Ayoub, Michael Kishinevsky, Ahmed Abousamra, Ümit Y. Ogras:
Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration. 1-9 - Hadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng:
VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis. 1-7 - Sina Asadi, M. Hassan Najafi, Mohsen Imani:
CORLD: In-Stream Correlation Manipulation for Low-Discrepancy Stochastic Computing. 1-9 - Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip. 1-9 - Elbruz Ozen, Alex Orailoglu:
Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs. 1-8 - Shiqing Li, Di Liu, Weichen Liu:
Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs. 1-9 - Yawen Wu, Dewen Zeng, Zhepeng Wang, Yi Sheng, Lei Yang, Alaina J. James, Yiyu Shi, Jingtong Hu:
Federated Contrastive Learning for Dermatological Disease Diagnosis via On-device Learning (Invited Paper). 1-7 - Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. 1-9 - Chao-Yuan Huang, Yi-Chen Chang, Ming-Jer Tsai, Tsung-Yi Ho:
An Optimal Algorithm for Splitter and Buffer Insertion in Adiabatic Quantum-Flux-Parametron Circuits. 1-8 - Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism. 1-9 - Ran Chen, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Bei Yu, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao:
A Unified Framework for Layout Pattern Analysis with Deep Causal Estimation. 1-9 - Hsiao-Yin Tseng, I-Wei Chiu, Mu-Ting Wu, James Chien-Mo Li:
Machine Learning-Based Test Pattern Generation for Neuromorphic Chips. 1-7 - Kathleen E. Hamilton, Emily Lynn, Vicente Leyton-Ortega, Swarnadeep Majumder, Raphael C. Pooser:
Mode connectivity in the QCBM loss landscape: ICCAD Special Session Paper. 1-9 - Dingcheng Yang, Wenjian Yu, Yuanbo Guo, Wenjie Liang:
CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction. 1-9 - Emmanuel Pescosta, Georg Weissenbacher, Florian Zuleger:
Bounded Model Checking of Speculative Non-Interference. 1-9 - Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Chia-Lin Yang, Hussam Amrouch:
Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization. 1-9 - Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu:
DevelSet: Deep Neural Level Set for Instant Mask Optimization. 1-9 - Nagadastagiri Challapalle, Karthik Swaminathan, Nandhini Chandramoorthy, Vijaykrishnan Narayanan:
Crossbar based Processing in Memory Accelerator Architecture for Graph Convolutional Networks. 1-9 - Ilya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López, José Flich, Carles Hernández:
Improving the Robustness of Redundant Execution with Register File Randomization. 1-9 - Bulbul Ahmed, Fahim Rahman, Nick Hooten, Farimah Farahmandi, Mark M. Tehranipoor:
AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow. 1-9 - Di Gao, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo:
Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training. 1-9 - Marco Pistoia, Syed Farhan Ahmad, Akshay Ajagekar, Alexander Buts, Shouvanik Chakrabarti, Dylan Herman, Shaohan Hu, Andrew Jena, Pierre Minssen, Pradeep Niroula, Arthur G. Rattew, Yue Sun, Romina Yalovetzky:
Quantum Machine Learning for Finance ICCAD Special Session Paper. 1-9 - Zhiding Liang, Zhepeng Wang, Junhuan Yang, Lei Yang, Yiyu Shi, Weiwen Jiang:
Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow (Invited Paper). 1-7 - Myeonggu Kang, Hyein Shin, Jaekang Shin, Lee-Sup Kim:
A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators. 1-9 - Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong:
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. 1-9 - Kazi Asifuzzaman, Mohamed Abuelala, Mohamed Hassan, Francisco J. Cazorla:
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems. 1-9 - Serena Curzel, Nicolas Bohm Agostini, Shihao Song, Ismet Dagli, Ankur Limaye, Cheng Tan, Marco Minutoli, Vito Giovanni Castellana, Vinay Amatya, Joseph B. Manzano, Anup Das, Fabrizio Ferrandi, Antonino Tumeo:
Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators. 1-7 - Yuyang Wang, Kwang-Ting Cheng:
Traffic-Adaptive Power Reconfiguration for Energy-Efficient and Energy-Proportional Optical Interconnects. 1-9 - Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu:
UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. 1-9 - Fangda Zuo, Mengchu Li, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann:
Relative-Scheduling-Based High-Level Synthesis for Flow-Based Microfluidic Biochips. 1-9 - Abdullah Ash-Saki, Aakarshitha Suresh, Rasit Onur Topaloglu, Swaroop Ghosh:
Split Compilation for Security of Quantum Circuits. 1-7 - Marina Neseem, Sherief Reda:
AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices. 1-9 - Yeseong Kim, Mohsen Imani, Saransh Gupta, Minxuan Zhou, Tajana Simunic Rosing:
Massively Parallel Big Data Classification on a Programmable Processing In-Memory Architecture. 1-9 - Dan Zheng, Xinshi Zang, Martin D. F. Wong:
TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA Systems. 1-8 - Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen:
Automatic Routability Predictor Development Using Neural Architecture Search. 1-9 - Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu:
Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach. 1-9 - Hassan Nassar, Hanna AlZughbi, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel:
LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs. 1-9 - Majid Sabbagh, Yunsi Fei, David R. Kaeli:
GPU Overdrive Fault Attacks on Neural Networks. 1-8 - Yang Bai, Xufeng Yao, Qi Sun, Bei Yu:
AutoGTCO: Graph and Tensor Co-Optimize for Image Recognition with Transformers on GPU. 1-9 - Hussam Amrouch, Jian-Jia Chen, Kaushik Roy, Yuan Xie, Indranil Chakraborty, Wenqin Huangfu, Ling Liang, Fengbin Tu, Cheng Wang, Mikail Yayla:
Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper. 1-9 - Zhiqiang Liu, Wenjian Yu:
pGRASS-Solver: A Parallel Iterative Solver for Scalable Power Grid Analysis Based on Graph Spectral Sparsification. 1-9 - Sebastian Brandhofer, Ilia Polian, Hans Peter Büchler:
Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms. 1-7 - Ourania Spantidi, Georgios Zervakis, Iraklis Anagnostopoulos, Hussam Amrouch, Jörg Henkel:
Positive/Negative Approximate Multipliers for DNN Accelerators. 1-9 - Yen-Chun Fang, Shao-Lun Huang, Chi-An Wu, Chung-Han Chou, Chih-Jen Hsu, WoeiTzy Jong, Kei-Yong Khoo:
2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper. 1-6 - Feng Wang, Guangyu Sun, Guojie Luo:
SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes. 1-9 - Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan:
OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. 1-9 - Kaveh Shamsi, Yier Jin:
Circuit Deobfuscation from Power Side-Channels using Pseudo-Boolean SAT. 1-9 - Zhihui Gao, Ang Li, Yunfan Gao, Bing Li, Yu Wang, Yiran Chen:
FedSwap: A Federated Learning based 5G Decentralized Dynamic Spectrum Access System. 1-6 - Sungju Ryu, Youngtaek Oh, Jae-Joon Kim:
Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow. 1-9 - Subhajit Dutta Chowdhury, Kaixin Yang, Pierluigi Nuzzo:
ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineering. 1-9 - Nathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany:
IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs. 1-9 - Shihao Song, M. Lakshmi Varshika, Anup Das, Nagarajan Kandasamy:
A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware. 1-9 - Fuxun Yu, Shawn Bray, Di Wang, Longfei Shangguan, Xulong Tang, Chenchen Liu, Xiang Chen:
Automated Runtime-Aware Scheduling for Multi-Tenant DNN Inference on GPU. 1-9 - Azat Azamat, Faaiz Asim, Jongeun Lee:
Quarry: Quantization-based ADC Reduction for ReRAM-based Deep Neural Network Accelerators. 1-7 - Weizheng Xu, Ashutosh Pattnaik, Geng Yuan, Yanzhi Wang, Youtao Zhang, Xulong Tang:
ScaleDNN: Data Movement Aware DNN Training on Multi-GPU. 1-9 - Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Critical Path Generation with Path Constraints. 1-9 - He-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko:
A Circuit-Based SAT Solver for Logic Synthesis. 1-6 - Elias Trommer, Bernd Waschneck, Akash Kumar:
dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference. 1-9 - Ching-Cheng Wang, Wai-Kei Mak:
A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits. 1-9 - Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu:
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. 1-9 - Chengyu Zhang, Minquan Sun, Jianwen Li, Ting Su, Geguang Pu:
Feedback-Guided Circuit Structure Mutation for Testing Hardware Model Checkers. 1-9 - Boyang Zhang, Yang Sui, Lingyi Huang, Siyu Liao, Chunhua Deng, Bo Yuan:
Algorithm and Hardware Co-design for Deep Learning-powered Channel Decoder: A Case Study. 1-6 - Aqeeb Iqbal Arka, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks. 1-9 - Yoo-Seung Won, Soham Chatterjee, Dirmanto Jap, Arindam Basu, Shivam Bhasin:
DeepFreeze: Cold Boot Attacks and High Fidelity Model Recovery on Commercial EdgeML Device. 1-9 - Sanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Gauthaman Murali, Mark Nelson, Sung Kyu Lim, Krishnendu Chakrabarty:
ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs. 1-9 - Kazuo Aoyama, Hiroshi Sawada:
Acceleration Method for Learning Fine-Layered Optical Neural Networks. 1-9 - Yu-Neng Wang, Yun-Rong Luo, Po-Chun Chien, Ping-Lun Wang, Hao-Ren Wang, Wan-Hsuan Lin, Jie-Hong Roland Jiang, Chung-Yang (Ric) Huang:
Compatible Equivalence Checking of X-Valued Circuits. 1-9 - Mahabubul Alam, Satwik Kundu, Rasit Onur Topaloglu, Swaroop Ghosh:
Quantum-Classical Hybrid Machine Learning for Image Classification (ICCAD Special Session Paper). 1-7 - Fangzhou Wang, Lixin Liu, Jingsong Chen, Jinwei Liu, Xinshi Zang, Martin D. F. Wong:
Starfish: An Efficient P&R Co-Optimization Engine with A*-based Partial Rerouting. 1-9 - Hao Geng, Fan Yang, Xuan Zeng, Bei Yu:
When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning. 1-8 - Shouvanik Chakrabarti, Xuchen You, Xiaodi Wu:
ICCAD Special Session Paper: Quantum Variational Methods for Quantum Applications. 1-7 - Weilin Luo, Hai Wan, Hongzhen Zhong, Ou Wei, Biqing Fang, Xiaotong Song:
An Efficient Two-phase Method for Prime Compilation of Non-clausal Boolean Formulae. 1-9 - Ghasem Pasandi, Sreedhar Pratty, David Brown, Yanqing Zhang, Haoxing Ren, Brucek Khailany:
2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting. 1-6 - Seungkyu Choi, Jaekang Shin, Lee-Sup Kim:
A Convergence Monitoring Method for DNN Training of On-Device Task Adaptation. 1-9 - Tsung-Wei Huang, Yu-Guang Chen, Chun-Yao Wang, Takashi Sato:
Overview of 2021 CAD Contest at ICCAD. 1-3 - Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique:
ReSpawn: Energy-Efficient Fault-Tolerance for Spiking Neural Networks considering Unreliable Memories. 1-9 - Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok:
An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits. 1-9 - Muhammad Rashedul Haq Rashed, Sumit Kumar Jha, Rickard Ewetz:
Hybrid Analog-Digital In-Memory Computing. 1-9 - Hongwu Peng, Shiyang Chen, Zhepeng Wang, Junhuan Yang, Scott A. Weitze, Tong Geng, Ang Li, Jinbo Bi, Minghu Song, Weiwen Jiang, Hang Liu, Caiwen Ding:
Optimizing FPGA-based Accelerator Design for Large-Scale Molecular Similarity Search (Special Session Paper). 1-7 - Wei Zhao, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Jie Xu, Chunyan Li, Gaoxiang Xu, Yiran Chen:
MORE2: Morphable Encryption and Encoding for Secure NVM. 1-8 - Yasasvi V. Peruvemba, Shubham Rai, Kapil Ahuja, Akash Kumar:
RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis. 1-9 - Arman Roohi, MohammadReza Taheri, Shaahin Angizi, Deliang Fan:
RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems. 1-9 - Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar:
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. 1-9 - W. Rhett Davis, Paul D. Franzon, Luis Francisco, Billy Huggins, Rajeev Jain:
Fast and Accurate PPA Modeling with Transfer Learning. 1-8 - Xuanyi Li, Chen Li, Yang Guo, Rachata Ausavarungnirun:
Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPU. 1-9 - Osaze Shears, Kangjun Bai, Lingjia Liu, Yang Yi:
A Hybrid FPGA-ASIC Delayed Feedback Reservoir System to Enable Spectrum Sensing/Sharing for Low Power IoT Devices ICCAD Special Session Paper. 1-9 - Kyeonghyeon Baek, Taewhan Kim:
Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis. 1-8 - Francesco Restuccia, Andres Meza, Ryan Kastner:
Aker: A Design and Verification Framework for Safe and Secure SoC Access Control. 1-9 - Muhammad Shafique, Alberto Marchisio, Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif:
Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework ICCAD Special Session Paper. 1-9 - Jeremy Blackstone, Debayan Das, Alric Althoff, Shreyas Sen, Ryan Kastner:
iSTELLAR: intermittent Signature aTtenuation Embedded CRYPTO with Low-Level metAl Routing. 1-9 - Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Ravi Varadarajan:
METRICS2.1 and Flow Tuning in the IEEE CEDA Robust Design Flow and OpenROAD ICCAD Special Session Paper. 1-9 - Dajiang Liu, Ting Liu, Xingyu Mo, Jiaxing Shang, Shouyi Yin:
Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs. 1-9 - Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung Kyu Lim, Ozgur Sinanoglu, Ramesh Karri:
Security Closure of Physical Layouts ICCAD Special Session Paper. 1-9 - Jai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Che-Li Lin, Chen-Fa Tsai:
Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs. 1-8 - Imam Al Razi, Quang Le, H. Alan Mantooth, Yarui Peng:
Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation. 1-8 - Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini:
Banshee: A Fast LLVM-Based RISC-V Binary Translator. 1-9 - Seetal Potluri, Aydin Aysu:
Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware. 1-8 - Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Exploring eFPGA-based Redaction for IP Protection. 1-9 - Yongan Zhang, Haoran You, Yonggan Fu, Tong Geng, Ang Li, Yingyan Lin:
G-CoS: GNN-Accelerator Co-Search Towards Both Better Accuracy and Efficiency. 1-9 - Zih-Yao Lin, Yao-Wen Chang:
A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement. 1-6 - Md. Shohidul Islam, Ihsen Alouani, Khaled N. Khasawneh:
Lower Voltage for Higher Security: Using Voltage Overscaling to Secure Deep Neural Networks. 1-9 - Shaoze Fan, Ningyuan Cao, Shun Zhang, Jing Li, Xiaoxiao Guo, Xin Zhang:
From Specification to Topology: Automatic Power Converter Design via Reinforcement Learning. 1-9 - Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo:
DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. 1-6 - Bochen Tan, Jason Cong:
Optimal Qubit Mapping with Simultaneous Gate Absorption ICCAD Special Session Paper. 1-8 - Ali Aghdaei, Zhiqiang Zhao, Zhuo Feng:
HyperSF: Spectral Hypergraph Coarsening via Flow-based Local Clustering. 1-9 - Mojan Javaheripi, Farinaz Koushanfar:
HASHTAG: Hash Signatures for Online Detection of Fault-Injection Attacks on Deep Neural Networks. 1-9 - Nitthilan Kannappan Jayakodi, Janardhan Rao Doppa, Partha Pratim Pande:
A General Hardware and Software Co-Design Framework for Energy-Efficient Edge AI. 1-7 - Wei-Kai Liu, Ming-Hung Chen, Chia-Ming Chang, Chen-Chia Chang, Yao-Wen Chang:
Time-Division Multiplexing Based System-Level FPGA Routing. 1-6 - Biresh Kumar Joardar, Aqeeb Iqbal Arka, Janardhan Rao Doppa, Partha Pratim Pande, Hai Li, Krishnendu Chakrabarty:
Heterogeneous Manycore Architectures Enabled by Processing-in-Memory for Deep Learning: From CNNs to GNNs: (ICCAD Special Session Paper). 1-7 - Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor:
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. 1-9 - Chang Meng, Zhiyuan Xiang, Niyiqiu Liu, Yixuan Hu, Jiahao Song, Runsheng Wang, Ru Huang, Weikang Qian:
DALTA: A Decomposition-based Approximate Lookup Table Architecture. 1-8 - Shiju Lin, Jinwei Liu, Martin D. F. Wong:
GAMER: GPU Accelerated Maze Routing. 1-8 - Rongjian Liang, Jinwook Jung, Hua Xiang, Lakshmi N. Reddy, Alexey Lvov, Jiang Hu, Gi-Joon Nam:
FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer. 1-9 - Guoqi Xie, Xiangzhen Xiao, Hong Liu, Renfa Li, Wanli Chang:
Robust Time-Sensitive Networking with Delay Bound Analyses. 1-9 - Vidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar:
BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology. 1-8 - Nanda K. Unnikrishnan, Keshab K. Parhi:
LayerPipe: Accelerating Deep Neural Network Training by Intra-Layer and Inter-Layer Gradient Pipelining and Multiprocessor Scheduling. 1-8 - Kai-Shun Hu, Tao-Chun Yu, Ming-Jen Yang, Cindy Chin-Fang Shen:
2021 ICCAD CAD Contest Problem B: Routing with Cell Movement Advanced: Invited Paper. 1-5 - Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Yongbiao Chen, Li Jiang:
Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator. 1-9 - Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestor E. Evmorfopoulos, Sachin S. Sapatnekar:
Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections. 1-8 - Cheng Zeng, Fan Yang, Xuan Zeng:
Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression. 1-8 - Mahdi Nazemi, Hitarth Kanakia, Massoud Pedram:
Heuristics for Million-scale Two-level Logic Minimization. 1-7 - Yitu Wang, Zhenhua Zhu, Fan Chen, Mingyuan Ma, Guohao Dai, Yu Wang, Hai Li, Yiran Chen:
Rerec: In-ReRAM Acceleration with Access-Aware Mapping for Personalized Recommendation. 1-9 - Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang:
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. 1-9 - Zhepeng Wang, Zhiding Liang, Shanglin Zhou, Caiwen Ding, Yiyu Shi, Weiwen Jiang:
Exploration of Quantum Neural Architecture by Mixing Quantum Neuron Designs: (Invited Paper). 1-7 - Xing Huang, Youlin Pan, Zhen Chen, Wenzhong Guo, Robert Wille, Tsung-Yi Ho, Ulf Schlichtmann:
BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems. 1-8 - Matthew M. Ziegler, Jihye Kwon, Hung-Yi Liu, Luca P. Carloni:
Online and Offline Machine Learning for Industrial Design Flow Tuning: (Invited - ICCAD Special Session Paper). 1-9 - Hussam Amrouch, Di Gao, Xiaobo Sharon Hu, Arman Kazemi, Ann Franchesca Laguna, Kai Ni, Michael T. Niemier, Mohammad Mehdi Sharifi, Simon Thomann, Xunzhao Yin, Cheng Zhuo:
ICCAD Tutorial Session Paper Ferroelectric FET Technology and Applications: From Devices to Systems. 1-8 - Mehran Goli, Rolf Drechsler:
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs. 1-8 - Xuan Wang, Zhufei Chu, Weikang Qian:
MinSC: An Exact Synthesis-Based Method for Minimal-Area Stochastic Circuits under Relaxed Error Bound. 1-9 - Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu:
Graph Learning-Based Arithmetic Block Identification. 1-8 - Yuwei Hu, Yixiao Du, Ecenur Ustun, Zhiru Zhang:
GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs. 1-9 - Priyanka Golia, Friedrich Slivovsky, Subhajit Roy, Kuldeep S. Meel:
Engineering an Efficient Boolean Functional Synthesis Engine. 1-9 - Yu Zeng, Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. 1-9 - Necati Uysal, Rickard Ewetz:
An OCV-Aware Clock Tree Synthesis Methodology. 1-9 - Panjie Qi, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Hongwu Peng, Shaoyi Huang, Zhenglun Kong, Yuhong Song, Bingbing Li:
Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization. 1-9 - Jiaxi Zhang, Liwei Ni, Shenggen Zheng, Hao Liu, Xiangfu Zou, Feng Wang, Guojie Luo:
Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning. 1-9 - Shuhang Zhang, Hai Li, Ulf Schlichtmann:
Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing. 1-9 - Haoxing Ren, Saad Godil, Brucek Khailany, Robert Kirby, Haiguang Liao, Siddhartha Nath, Jonathan Raiman, Rajarshi Roy:
Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper. 1-6 - Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, Martin D. F. Wong:
Hotspot Detection via Multi-task Learning and Transformer Encoder. 1-8 - Fu-Yu Chuang, Yao-Wen Chang:
On-chip Optical Routing with Waveguide Matching Constraints. 1-6
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