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Ilya Tuzov
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2020 – today
- 2023
- [c13]Ilya Tuzov, David de Andrés, Juan-Carlos Ruiz-Garcia, Carles Hernández:
BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes. DATE 2023: 1-6 - [c12]Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric:
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. ETS 2023: 1-10 - 2022
- [c11]Ali Asghar, Amanda Katherine Robillard, Ilya Tuzov, Andreas Becher, Daniel Ziener:
Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. ARCS 2022: 132-147 - [c10]Ilya Tuzov, David de Andrés, Juan Carlos Ruiz:
Reversing FPGA architectures for speeding up fault injection: does it pay? EDCC 2022: 81-88 - 2021
- [c9]Ilya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López, José Flich, Carles Hernández:
Improving the Robustness of Redundant Execution with Register File Randomization. ICCAD 2021: 1-9 - 2020
- [c8]Ilya Tuzov, David de Andrés, Juan Carlos Ruiz:
Improving Robustness-Aware Design Space Exploration for FPGA-Based Systems. EDCC 2020: 1-8
2010 – 2019
- 2019
- [j2]Ilya Tuzov, David de Andrés, Juan Carlos Ruiz:
Simulating the effects of logic faults in implementation-level VITAL-compliant models. Computing 101(2): 77-96 (2019) - [c7]Ilya Tuzov, David de Andrés, Juan Carlos Ruiz:
Robustness-Aware Design Space Exploration Through Iterative Refinement of D-Optimal Designs. EDCC 2019: 23-30 - 2018
- [j1]Ilya Tuzov, David de Andrés, Juan Carlos Ruiz:
Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study. J. Parallel Distributed Comput. 112: 84-96 (2018) - [c6]Ilya Tuzov, David de Andrés, Juan Carlos Ruiz:
DAVOS: EDA Toolkit for Dependability Assessment, Verification, Optimisation and Selection of Hardware Models. DSN 2018: 322-329 - [c5]Ilya Tuzov, David de Andrés, Juan Carlos Ruiz:
Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection. EDCC 2018: 1-8 - [c4]Ilya Tuzov, David de Andrés, Juan Carlos Ruiz:
Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection. LADC 2018: 97-106 - 2017
- [c3]Ilya Tuzov, David de Andrés, Juan Carlos Ruiz:
Dependability-Aware Design Space Exploration for Optimal Synthesis Parameters Tuning. DSN 2017: 121-132 - [c2]Ilya Tuzov, Juan Carlos Ruiz, David de Andrés:
Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level. EDCC 2017: 10-17 - 2016
- [c1]Ilya Tuzov, Juan Carlos Ruiz, David de Andrés, Pedro J. Gil:
Speeding-Up Simulation-Based Fault Injection of Complex HDL Models. LADC 2016: 51-60
Coauthor Index
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