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2020 – today
- 2024
[j6]Jens Trautmann
, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Trans. Reconfigurable Technol. Syst. 17(2): 24:1-24:28 (2024)- [c23]Ali Asghar, Andreas Becher, Daniel Ziener:
Short Paper: Analysis of Vivado implementation strategies regarding side-channel leakage for FPGA-based AES implementations. HASP@MICRO 2024: 45-49 - 2022
- [b1]Andreas Becher:
Near-Data Query Processing on Heterogeneous FPGA-based Systems. University of Erlangen-Nuremberg, Germany, 2022 - [j5]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. 64(3): 89-98 (2022) - [j4]Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(1): 7:1-7:27 (2022) - [c22]Ali Asghar, Amanda Katherine Robillard, Ilya Tuzov, Andreas Becher, Daniel Ziener:
Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. ARCS 2022: 132-147 - [c21]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS 2022: 65-74 - [c20]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. DATE 2022: 250-255 - [c19]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL 2022: 94-100 - [i6]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. CoRR abs/2205.05464 (2022) - [i5]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR abs/2206.10368 (2022) - 2021
- [j3]Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich:
Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum 21(1): 55-64 (2021) - [c18]Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich:
Choice - A Tunable PUF-Design for FPGAs. FPL 2021: 38-44 - [i4]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR abs/2105.05588 (2021) - 2020
- [c17]Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Klaus Meyer-Wegener:
The ReProVide query-sequence optimization in a hardware-accelerated DBMS. DaMoN 2020: 17:1-17:3 - [c16]Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich:
SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT 2020: 639-642 - [c15]Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich:
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. HOST 2020: 102-110 - [i3]Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener:
Query-Sequence Optimization on a Reconfigurable Hardware-Accelerated System. CoRR abs/2001.10719 (2020) - [i2]Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich:
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. CoRR abs/2004.09453 (2020) - [i1]Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener:
The ReProVide Query-Sequence Optimization in a Hardware-Accelerated DBMS. CoRR abs/2005.01511 (2020)
2010 – 2019
- 2019
- [c14]Andreas Becher, Achim Herrmann, Stefan Wildermann, Jürgen Teich:
ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. BTW (Workshops) 2019: 51-70 - [c13]Andreas Becher, Jürgen Teich:
In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing. DaMoN 2019: 20:1-20:3 - [c12]Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. ReConFig 2019: 1-8 - 2018
- [j2]Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann:
Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum 18(3): 145-156 (2018) - [c11]Andreas Becher, Stefan Wildermann, Jürgen Teich:
Optimistic regular expression matching on FPGAs for near-data processing. DaMoN 2018: 4:1-4:3 - [c10]Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Can Approximate Computing Reduce Power Consumption on FPGAs? ICECS 2018: 841-844 - [c9]Franz-Josef Streit, Martín Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich:
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. ReConFig 2018: 1-8 - 2017
- [c8]Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, Stefan Wildermann:
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. SCOPES 2017: 89-92 - 2016
- [j1]Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber:
FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Trans. Reconfigurable Technol. Syst. 9(4): 25:1-25:24 (2016) - [c7]Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich:
A LUT-Based Approximate Adder. FCCM 2016: 27 - [c6]Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener:
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT 2016: 213-216 - [c5]Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann:
Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. ReConFig 2016: 1-7 - [c4]Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich:
ReOrder: Runtime datapath generation for high-throughput multi-stream processing. ReConFig 2016: 1-8 - 2015
- [c3]Robért Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, Albert Heuberger:
Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. AHS 2015: 1-8 - [c2]Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich:
A co-design approach for accelerated SQL query processing via FPGA-based data filtering. FPT 2015: 192-195 - 2014
- [c1]Andreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich:
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. FPL 2014: 1-8
Coauthor Index
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