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ORCIDJürgen Teich
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- affiliation: University of Erlangen-Nuremberg, Germany
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2020 – today
- 2024
[j126]Martín Letras
, Joachim Falk, Jürgen Teich:
Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems. IEEE Access 12: 39748-39769 (2024)- [j125]Christian Heidorn, Muhammad Sabih, Nicolai Meyerhöfer, Christian Schinabeck, Jürgen Teich, Frank Hannig:
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks. Int. J. Parallel Program. 52(1-2): 40-58 (2024) - [j124]Jan Spieck, Stefan Wildermann, Jürgen Teich:
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs. ACM Trans. Design Autom. Electr. Syst. 29(4): 1-43 (2024) - [j123]Jens Trautmann, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Trans. Reconfigurable Technol. Syst. 17(2): 24:1-24:28 (2024) - [c499]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. ARC 2024: 3-18 - [c498]Dominik Walter, Thomas Adamtschuk, Frank Hannig, Jürgen Teich:
Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays. ASAP 2024: 97-106 - [c497]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. DATE 2024: 1-2 - [c496]Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jürgen Teich:
Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. DATE 2024: 1-2 - [c495]Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich:
ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs. DDECS 2024: 79-85 - [c494]Nils Wilbert, Stefan Wildermann, Jürgen Teich:
To Keep or Not to Keep - The Volatility of Replacement Policy Metadata in Hybrid Caches. DIMES@SOSP 2024: 17-24 - [c493]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
DSL-Based SNN Accelerator Design Using Chisel. DSD 2024: 176-184 - [c492]Paul Krüger, Stefan Wildermann, Jürgen Teich:
CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets. EuroSec@EUROSYS 2024: 37-43 - [c491]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs. FPL 2024: 11-18 - [c490]Khalil Esper, Jürgen Teich:
History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs. NG-RES@HiPEAC 2024: 4:1-4:11 - [c489]Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich:
ALPACA: An Accelerator Chip for Nested Loop Programs. ISCAS 2024: 1-5 - [c488]Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich:
GRES: Guaranteed Remaining Energy Scheduling of Energy-harvesting Sensors by Quality Adaptation. MECO 2024: 1-5 - [c487]Abrarul Karim, Joachim Falk, Dennis Schmidt, Jürgen Teich:
Self-Powering Dataflow Networks - Concepts and Implementation. MEMOCODE 2024: 69-74 - [c486]Nils Wilbert, Stefan Wildermann, Jürgen Teich:
Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study. MEMSYS 2024: 257-269 - [c485]Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich:
Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. VEHITS 2024: 64-75 - [i45]Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich:
OpTC - A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. CoRR abs/2404.15833 (2024) - [i44]Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich:
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. CoRR abs/2407.10734 (2024) - [i43]Mark Deutel, Christopher Mutschler, Jürgen Teich:
microYOLO: Towards Single-Shot Object Detection on Microcontrollers. CoRR abs/2408.15865 (2024) - 2023
- [j122]Alberto Bosio, Mario Barbareschi, Alessandro Savino, Jie Han, Jürgen Teich:
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. IEEE Des. Test 40(3): 5-7 (2023) - [j121]Chetana Pradhan, Martín Letras, Jürgen Teich:
Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation. ACM Trans. Embed. Comput. Syst. 22(4): 73:1-73:24 (2023) - [j120]Jan Spieck, Stefan Wildermann, Jürgen Teich:
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. ACM Trans. Design Autom. Electr. Syst. 28(1): 4:1-4:40 (2023) - [j119]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. ACM Trans. Design Autom. Electr. Syst. 28(6): 98:1-98:20 (2023) - [c484]Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich:
An FPGA Avro Parser Generator for Accelerated Data Stream Processing. BTW 2023: 729-749 - [c483]Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng:
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES 2023: 11-20 - [c482]Pierre-Louis Sixdenier, Stefan Wildermann, Martin Ottens, Jürgen Teich:
Seque: Lean and Energy-aware Data Management for IoT Gateways. EDGE 2023: 133-139 - [c481]Muhammad Sabih, Mikail Yayla, Frank Hannig, Jürgen Teich, Jian-Jia Chen:
Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. EuroMLSys@EuroSys 2023: 87-93 - [c480]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. FPL 2023: 189-196 - [c479]Martín Letras, Joachim Falk, Jürgen Teich:
Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers. NG-RES@HiPEAC 2023: 6:1-6:13 - [c478]Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich:
RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. NG-RES@HiPEAC 2023: 7:1-7:16 - [c477]Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich:
Energy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression. MBMV 2023: 1-12 - [c476]Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann, Jürgen Teich:
Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. MEMOCODE 2023: 23-35 - [c475]Mark Deutel, Christopher Mutschler, Jürgen Teich:
μYOLO: Towards Single-Shot Object Detection on Microcontrollers. PKDD/ECML Workshops (5) 2023: 163-169 - [i42]Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich:
Augmented Random Search for Multi-Objective Bayesian Optimization of Neural Networks. CoRR abs/2305.14109 (2023) - [i41]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR abs/2306.12742 (2023) - [i40]Martín Letras, Joachim Falk, Jürgen Teich:
Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems. CoRR abs/2311.17473 (2023) - 2022
- [j118]Behnaz Pourmohseni, Stefan Wildermann, Fedor Smirnov, Paul E. Meyer, Jürgen Teich:
Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems. IEEE Access 10: 33787-33802 (2022) - [j117]Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende:
The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurr. Comput. Pract. Exp. 34(14) (2022) - [j116]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. 64(3): 89-98 (2022) - [j115]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3767-3778 (2022) - [j114]Jan Spieck, Stefan Wildermann, Jürgen Teich:
On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4289-4300 (2022) - [j113]Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich:
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2661-2666 (2022) - [j112]Jens Trautmann, Arthur Beckers, Lennert Wouters, Stefan Wildermann, Ingrid Verbauwhede, Jürgen Teich:
Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1): 345-366 (2022) - [j111]Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(1): 7:1-7:27 (2022) - [c474]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS 2022: 65-74 - [c473]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. DATE 2022: 250-255 - [c472]Muhammad Sabih, Frank Hannig, Jürgen Teich:
DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. EuroMLSys@EuroSys 2022: 109-115 - [c471]Jens Trautmann, Jürgen Teich, Stefan Wildermann:
Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. FCCM 2022: 1-9 - [c470]Patrick Plagwitz, Frank Hannig, Jürgen Teich:
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. FPL 2022: 17-23 - [c469]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL 2022: 94-100 - [c468]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. FPL 2022: 160-166 - [c467]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
Auto-Tuning of Raw Filters for FPGAs. FPL 2022: 167-175 - [c466]Muhammad Sabih, Ashutosh Mishra, Frank Hannig, Jürgen Teich:
MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. IGSC 2022: 1-8 - [c465]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study. NG-RES@HiPEAC 2022: 2:1-2:13 - [c464]Peter Brand, Benjamin Hackenberg, Joachim Falk, Jürgen Teich:
Grant Prediction-based Dynamic Power Management for 5G to Reduce Mobile Device Energy Consumption. IWCMC 2022: 647-652 - [c463]Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich:
Hardware-Aware Evolutionary Filter Pruning. SAMOS 2022: 283-299 - [c462]Pierre-Louis Sixdenier, Stefan Wildermann, Daniel Ziegler, Jürgen Teich:
SIDAM: A Design Space Exploration Framework for Multi-sensor Embedded Systems Powered by Energy Harvesting. SAMOS 2022: 329-345 - [i39]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. CoRR abs/2203.11028 (2022) - [i38]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. CoRR abs/2203.12437 (2022) - [i37]Chetana Pradhan, Martín Letras, Jürgen Teich:
Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation. CoRR abs/2204.02443 (2022) - [i36]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. CoRR abs/2205.05464 (2022) - [i35]Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich:
Deployment of Energy-Efficient Deep Learning Models on Cortex-M based Microcontrollers using Deep Compression. CoRR abs/2205.10369 (2022) - [i34]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR abs/2206.10368 (2022) - 2021
- [j110]Frank Hannig, Jürgen Teich:
Open Source Hardware. Computer 54(10): 111-115 (2021) - [j109]Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33(14) (2021) - [j108]Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich:
Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum 21(1): 55-64 (2021) - [j107]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. 18(3): 765-777 (2021) - [j106]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. 20(5): 49:1-49:31 (2021) - [j105]Faramarz Khosravi, Alexander Raß, Jürgen Teich:
Efficient Computation of Probabilistic Dominance in Multi-objective Optimization. ACM Trans. Evol. Learn. Optim. 1(4): 15:1-15:26 (2021) - [j104]Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich:
Adaptive Predictive Power Management for Mobile LTE Devices. IEEE Trans. Mob. Comput. 20(8): 2518-2535 (2021) - [j103]Martín Letras, Joachim Falk, Tobias Schwarzer, Jürgen Teich:
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements. ACM Trans. Design Autom. Electr. Syst. 26(3): 18:1-18:33 (2021) - [c461]Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich:
Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware. ARC 2021: 242-253 - [c460]Jürgen Teich, Pouya Mahmoody, Behnaz Pourmohseni, Sascha Roloff, Wolfgang Schröder-Preikschat, Stefan Wildermann:
Run-Time Enforcement of Non-functional Program Properties on MPSoCs. A Journey of Embedded and Cyber-Physical Systems 2021: 125-149 - [c459]Peter Brand, Joachim Falk, Tanja Maier, Jürgen Teich:
Simulating Realistic IoT Network Traffic Using Similarity-based DSE. CSCI 2021: 1377-1380 - [c458]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Approximate Logic Synthesis of Very Large Boolean Networks. DATE 2021: 1552-1557 - [c457]Muhammad Sabih, Frank Hannig, Jürgen Teich:
Fault-Tolerant Low-Precision DNNs using Explainable AI. DSN Workshops 2021: 166-174 - [c456]Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels:
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. ETS 2021: 1-10 - [c455]Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich:
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. FCCM 2021: 10-19 - [c454]Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich:
Choice - A Tunable PUF-Design for FPGAs. FPL 2021: 38-44 - [c453]Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich:
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. FPL 2021: 388 - [c452]Khalil Esper, Stefan Wildermann, Jürgen Teich:
A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper). NG-RES@HiPEAC 2021: 1:1-1:12 - [c451]Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor:
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. ICCAD 2021: 1-9 - [c450]Bo Qiao, Jürgen Teich, Frank Hannig:
An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. IPDPS Workshops 2021: 387-396 - [c449]Peter Brand, Joachim Falk, Eduard Potwigin, Jürgen Teich:
Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems. ISNCC 2021: 1-6 - [c448]Martín Letras, Joachim Falk, Jürgen Teich:
Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications. MBMV 2021: 1-11 - [c447]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. MEMOCODE 2021: 21-31 - [c446]Dominik Walter, Jürgen Teich:
LION: real-time I/O transfer control for massively parallel processor arrays. MEMOCODE 2021: 32-43 - [c445]Jan Spieck, Stefan Wildermann, Jürgen Teich:
Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs. MLCAD 2021: 1-6 - [c444]Jens Schlumberger, Stefan Wildermann, Jürgen Teich:
CORSICA: A Framework for Conducting Real-World Side-Channel Analysis. NTMS 2021: 1-5 - [c443]Armin Schuster, Christian Heidorn, Marcel Brand, Oliver Keszöcze, Jürgen Teich:
Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs Using Accuracy-Programmable Instruction Set Processors. PKDD/ECML Workshops (1) 2021: 375-389 - [c442]Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich:
Aarith: an arbitrary precision number library. SAC 2021: 529-534 - [c441]Stefan Groth, Jürgen Teich, Frank Hannig:
Efficient Application of Tensor Core Units for Convolving Images. SCOPES 2021: 1-6 - [i33]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR abs/2101.04395 (2021) - [i32]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR abs/2105.05588 (2021) - 2020
- [j102]Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, Jürgen Teich:
A bibliometric approach for detecting the gender gap in computer science. Commun. ACM 63(5): 74-80 (2020) - [j101]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig:
AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3202-3214 (2020) - [c440]Bo Wang, Aneek Imtiaz, Joachim Falk, Michael Glaß, Jürgen Teich:
Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-Specific Multi-core SoCs. ARCS 2020: 153-167 - [c439]Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich:
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. ASAP 2020: 157-164 - [c438]Jürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck, Stefan Wildermann:
Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. ASP-DAC 2020: 629-636 - [c437]Stefan Groth, Daniel Grünewald, Jürgen Teich, Frank Hannig:
A runtime system for finite element methods in a partitioned global address space. CF 2020: 39-48 - [c436]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich:
Probabilistic Error Propagation through Approximated Boolean Networks. DAC 2020: 1-6 - [c435]Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig:
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC 2020: 1-6 - [c434]Jan Spieck, Stefan Wildermann, Jürgen Teich:
Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. DAC 2020: 1-6 - [c433]Fedor Smirnov, Behnaz Pourmohseni, Jürgen Teich:
Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems. DATE 2020: 957-962 - [c432]Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich:
SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT 2020: 639-642 - [c431]Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende:
HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. Euro-Par Workshops 2020: 185-196 - [c430]Bertrand Simon, Joachim Falk, Nicole Megow, Jürgen Teich:
Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. NG-RES@HiPEAC 2020: 2:1-2:13 - [c429]Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich:
Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems. NG-RES@HiPEAC 2020: 5:1-5:14 - [c428]Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich:
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. HOST 2020: 102-110 - [c427]Dominik Walter, Michael Witterauf, Jürgen Teich:
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. MEMOCODE 2020: 1-11 - [c426]Bo Qiao, Oliver Reiche, Jürgen Teich, Frank Hannig:
Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. GPGPU@PPoPP 2020: 11-20 - [c425]Christian Heidorn, Frank Hannig, Jürgen Teich:
Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. SCOPES 2020: 26-31 - [c424]Bo Qiao, Oliver Reiche, M. Akif Özkan, Jürgen Teich, Frank Hannig:
Efficient parallel reduction on GPUs with Hipacc. SCOPES 2020: 58-61 - [c423]Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich:
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT 2020: 1-6 - [c422]Peter Brand, Muhammad Sabih, Joachim Falk, Jonathan Ah Sue, Jürgen Teich:
Clustering-Based Scenario-Aware LTE Grant Prediction. WCNC 2020: 1-7 - [p17]Christian Lengauer, Sven Apel, Matthias Bolten, Shigeru Chiba, Ulrich Rüde, Jürgen Teich, Armin Größlinger, Frank Hannig, Harald Köstler, Lisa Claus, Alexander Grebhahn, Stefan Groth, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt, Jonas Schmitt:
ExaStencils: Advanced Multigrid Solver Generation. Software for Exascale Computing 2020: 405-452 - [i31]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig:
AnyHLS: High-Level Synthesis with Partial Evaluation. CoRR abs/2002.05796 (2020) - [i30]Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich:
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. CoRR abs/2004.09453 (2020) - [i29]Muhammad Sabih, Frank Hannig, Jürgen Teich:
Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks. CoRR abs/2008.09072 (2020) - [i28]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: Wedding of OpenVX and DSL-based Code Generation. CoRR abs/2008.11476 (2020)
2010 – 2019
- 2019
- [b8]Sascha Roloff, Frank Hannig, Jürgen Teich:
Modeling and Simulation of Invasive Applications and Architectures. Computer Architecture and Design Methodologies, Springer 2019, ISBN 978-981-13-8386-1, pp. i-xv, 1-168 - [j100]Jürgen Teich, Franco Fummi:
Conference Reports: Recap of DATE 2019 in Florence, Italy. IEEE Des. Test 36(4): 59-61 (2019) - [j99]Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich:
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. J. Comput. 14(8): 541-556 (2019) - [j98]Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich:
Hard real-time application mapping reconfiguration for NoC-based many-core systems. Real Time Syst. 55(2): 433-469 (2019) - [j97]Fedor Smirnov, Behnaz Pourmohseni, Michael Glaß, Jürgen Teich:
IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of Embedded Systems. ACM Trans. Embed. Comput. Syst. 18(5s): 78:1-78:22 (2019) - [j96]Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich:
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. 5: 1-20 (2019) - [j95]Fedor Smirnov, Felix Reimann, Jürgen Teich, Michael Glaß:
Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks. ACM Trans. Design Autom. Electr. Syst. 24(1): 9:1-9:23 (2019) - [j94]Tobias Schwarzer, Joachim Falk, Simone Müller, Martín Letras, Christian Heidorn, Stefan Wildermann, Jürgen Teich:
Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization. ACM Trans. Design Autom. Electr. Syst. 24(3): 29:1-29:23 (2019) - [c421]Jörg Fickenscher, Frank Hannig, Jürgen Teich:
DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs. ARCS 2019: 71-86 - [c420]Andreas Becher, Achim Herrmann, Stefan Wildermann, Jürgen Teich:
ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. BTW (Workshops) 2019: 51-70 - [c419]Marcel Brand, Michael Witterauf, Frank Hannig, Jürgen Teich:
Anytime instructions for programmable accuracy floating-point arithmetic. CF 2019: 215-219 - [c418]Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich:
From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. CGO 2019: 242-253 - [c417]Andreas Becher, Jürgen Teich:
In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing. DaMoN 2019: 20:1-20:3 - [c416]Hananeh Aliee, Faramarz Khosravi, Jürgen Teich:
Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures. DSN 2019: 76-87 - [c415]Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich:
Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. ECRTS 2019: 12:1-12:24 - [c414]Jonathan Ah Sue, Peter Brand, Joachim Falk, Ralph Hasholzner, Jürgen Teich:
Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and Its Application to Mobile Devices. HCI (LBP) 2019: 119-139 - [c413]Jan Spieck, Stefan Wildermann, Tobias Schwarzer, Jürgen Teich, Michael Glaß:
Data-Driven Scenario-Based Application Mapping for Heterogeneous Many-Core Systems. MCSoC 2019: 334-341 - [c412]Michael Witterauf, Frank Hannig, Jürgen Teich:
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. MEMOCODE 2019: 8:1-8:10 - [c411]Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. ReConFig 2019: 1-8 - [c410]Behnaz Pourmohseni, Fedor Smirnov, Heba Khdr, Stefan Wildermann, Jürgen Teich, Jörg Henkel:
Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems. RTSS 2019: 220-232 - [c409]Stefan Groth, Christian Schmitt, Jürgen Teich, Frank Hannig:
SYCL Code Generation for Multigrid Methods. SCOPES 2019: 41-44 - [c408]Martín Letras, Joachim Falk, Tobias Schwarzer, Jürgen Teich:
On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures. SCOPES 2019: 63-71 - [c407]Fedor Smirnov, Behnaz Pourmohseni, Michael Glaß, Jürgen Teich:
Efficient Symbolic Routing Encoding for In-vehicle Network Optimization. SMARTGREENS/VEHITS (Selected Papers) 2019: 173-199 - [c406]Fedor Smirnov, Behnaz Pourmohseni, Michael Glaß, Jürgen Teich:
Variety-aware Routing Encoding for Efficient Design Space Exploration of Automotive Communication Networks. VEHITS 2019: 242-253 - [e11]Jürgen Teich, Franco Fummi:
Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019. IEEE 2019, ISBN 978-3-9819263-2-3 [contents] - [d2]Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich:
From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization. Version 1.0. Zenodo, 2019 [all versions]
- [d1]Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich:
From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization. Version 2.0. Zenodo, 2019 [all versions] - [i27]Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich:
Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. CoRR abs/1905.13503 (2019) - [i26]Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich:
Adaptive Predictive Power Management for Mobile LTE Devices. CoRR abs/1907.02774 (2019) - [i25]Faramarz Khosravi, Alexander Raß, Jürgen Teich:
Efficient Computation of Probabilistic Dominance in Robust Multi-Objective Optimization. CoRR abs/1910.08413 (2019) - [i24]Bertrand Simon, Joachim Falk, Nicole Megow, Jürgen Teich:
Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. CoRR abs/1912.09170 (2019) - 2018
- [b7]Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich:
Symbolic Parallelization of Nested Loop Programs. Springer 2018, ISBN 978-3-319-73908-3, pp. I-XII, 1-176 - [b6]Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, Jürgen Teich:
Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Computer Architecture and Design Methodologies, Springer 2018, ISBN 978-981-10-7355-7, pp. I-XXII, 1-164 - [j93]Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann:
Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum 18(3): 145-156 (2018) - [j92]Tulika Mitra, Jürgen Teich, Lothar Thiele:
Guest Editors' Introduction: Special Issue on Time-Critical Systems Design. IEEE Des. Test 35(2): 5-7 (2018) - [j91]Tulika Mitra, Jürgen Teich, Lothar Thiele:
Time-Critical Systems Design: A Survey. IEEE Des. Test 35(2): 8-26 (2018) - [j90]Tulika Mitra, Jürgen Teich, Lothar Thiele:
Guest Editors' Introduction: Special Issue on Time-Critical Systems Design Part II. IEEE Des. Test 35(4): 5-6 (2018) - [j89]Jorge Echavarria, Stefan Wildermann, Eduard Potwigin, Jürgen Teich:
Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. IEEE Embed. Syst. Lett. 10(2): 37-40 (2018) - [j88]Christian Schmitt, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Christian Lengauer:
Automating the Development of High-Performance Multigrid Solvers. Proc. IEEE 106(11): 1969-1984 (2018) - [j87]Christian Schmitt, Moritz Schmid, Sebastian Kuckuk, Harald Köstler, Jürgen Teich, Frank Hannig:
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Parallel Process. Lett. 28(4): 1850016:1-1850016:21 (2018) - [j86]Tobias Schwarzer, Andreas Weichslgartner, Michael Glaß, Stefan Wildermann, Peter Brand, Jürgen Teich:
Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 297-310 (2018) - [j85]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. 17(2): 31:1-31:27 (2018) - [j84]Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich:
A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. ACM Trans. Embed. Comput. Syst. 17(5): 89:1-89:25 (2018) - [j83]Oliver Reiche, M. Akif Ozkan, Frank Hannig, Jürgen Teich, Moritz Schmid:
Loop Parallelization Techniques for FPGA Accelerator Synthesis. J. Signal Process. Syst. 90(1): 3-27 (2018) - [c405]Ayesha Afzal, Christian Schmitt, Samer Alhaddad, Yevgen Grynko, Jürgen Teich, Jens Förstner, Frank Hannig:
Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study. ASAP 2018: 1-8 - [c404]Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP 2018: 1-9 - [c403]Faramarz Khosravi, Michael Borst, Jürgen Teich:
Probabilistic Dominance in Robust Multi-Objective Optimization. CEC 2018: 1-6 - [c402]Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jürgen Teich, Michael Glaß:
Architecture decomposition in system synthesis of heterogeneous many-core systems. DAC 2018: 175:1-175:6 - [c401]Andreas Becher, Stefan Wildermann, Jürgen Teich:
Optimistic regular expression matching on FPGAs for near-data processing. DaMoN 2018: 4:1-4:3 - [c400]Jörg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa:
Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. DATE 2018: 443-448 - [c399]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. FPT 2018: 326-329 - [c398]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Design space exploration of multi-output logic function approximations. ICCAD 2018: 52 - [c397]Jörg Henkel, Jürgen Teich, Stefan Wildermann, Hussam Amrouch:
Dynamic resource management for heterogeneous many-cores. ICCAD 2018: 60 - [c396]Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Can Approximate Computing Reduce Power Consumption on FPGAs? ICECS 2018: 841-844 - [c395]Tobias Schwarzer, Sascha Roloff, Valentina Richthammer, Rami Khaldi, Stefan Wildermann, Michael Glaß, Jürgen Teich:
On the Complexity of Mapping Feasibility in Many-Core Architectures. MCSoC 2018: 176-183 - [c394]Michael Witterauf, Jürgen Teich:
Run-time Requirement Enforcement for Loop Programs on Processor Arrays. MEMOCODE 2018: 22-32 - [c393]Franz-Josef Streit, Martín Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich:
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. ReConFig 2018: 1-8 - [c392]Daniel Ziener, Jutta Pirkl, Jürgen Teich:
Configuration Tampering of BRAM-based AES Implementations on FPGAs. ReConFig 2018: 1-7 - [c391]Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich:
Reinforcement Learning for Power-Efficient Grant Prediction in LTE. SCOPES 2018: 18-26 - [c390]Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich:
Automatic Kernel Fusion for Image Processing DSLs. SCOPES 2018: 76-85 - [c389]Fedor Smirnov, Felix Reimann, Jürgen Teich, Zhao Han, Michael Glaß:
Automatic Optimization of Redundant Message Routings in Automotive Networks. SCOPES 2018: 90-99 - [c388]Jörg Fickenscher, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa:
Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. VEHITS 2018: 298-306 - [c387]Jonathan Ah Sue, Peter Brand, Johannes Brendel, Ralph Hasholzner, Joachim Falk, Jürgen Teich:
A predictive dynamic power management for LTE-Advanced mobile devices. WCNC 2018: 1-6 - 2017
- [j82]Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Ulrich Rüde, Christian Lengauer:
A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms. Int. J. Comput. Sci. Eng. 14(2): 150-163 (2017) - [j81]Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner:
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. Integr. 59: 98-108 (2017) - [j80]Zhenmin Li, HeeJong Park, Avinash Malik, Kevin I-Kai Wang, Zoran Salcic, Boris Kuzmin, Michael Glaß, Jürgen Teich:
Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture. J. Syst. Archit. 74: 30-45 (2017) - [j79]Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jan Heisswolf, Jürgen Becker, Andreas Weichslgartner, Jürgen Teich:
Efficient task spawning for shared memory and message passing in many-core architectures. J. Syst. Archit. 77: 72-82 (2017) - [j78]Birgit Vogel-Heuser, Stefan Wildermann, Jürgen Teich:
Towards the co-evolution of industrial products and its production systems by combining models from development and hardware/software deployment in cyber-physical systems. Prod. Eng. 11(6): 687-694 (2017) - [j77]Hananeh Aliee, Emanuele Borgonovo, Michael Glaß, Jürgen Teich:
On the Boolean extension of the Birnbaum importance to non-coherent systems. Reliab. Eng. Syst. Saf. 160: 191-200 (2017) - [j76]Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel:
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Trans. Computers 66(3): 488-501 (2017) - [j75]Zoran Salcic, HeeJong Park, Jürgen Teich, Avinash Malik, Muhammad Nadeem:
Noc-HMP: A Heterogeneous Multicore Processor for Embedded Systems Designed in SystemJ. ACM Trans. Design Autom. Electr. Syst. 22(4): 73:1-73:25 (2017) - [j74]Faramarz Khosravi, Michael Glaß, Jürgen Teich:
Automatic Reliability Analysis in the Presence of Probabilistic Common Cause Failures. IEEE Trans. Reliab. 66(2): 319-338 (2017) - [j73]Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, Dibyendu Ghoshal:
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. 89(2): 225-242 (2017) - [c386]M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich:
Hardware design and analysis of efficient loop coarsening and border handling for image processing. ASAP 2017: 155-163 - [c385]Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich:
Efficiency in ILP processing by using orthogonality. ASAP 2017: 207 - [c384]Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich:
Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks. DAC 2017: 48:1-48:6 - [c383]Behnaz Pourmohseni, Michael Glaß, Jürgen Teich:
Automatic operating point distillation for hybrid mapping methodologies. DATE 2017: 1135-1140 - [c382]Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich:
Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networks. DATE 2017: 1643-1646 - [c381]Sascha Roloff, Frank Hannig, Jürgen Teich:
High performance network-on-chip simulation by interval-based timing predictions. ESTIMedia 2017: 2-11 - [c380]Faramarz Khosravi, Hananeh Aliee, Jürgen Teich:
System-level reliability analysis considering imperfect fault coverage. ESTIMedia 2017: 68-77 - [c379]Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig:
Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). ICCAD 2017: 1026-1033 - [c378]Franz-Josef Streit, Martín Letras, Matthias Schid, Joachim Falk, Stefan Wildermann, Jürgen Teich:
High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems. ICDSC 2017: 174-179 - [c377]Jörg Fickenscher, Sebastian Reinhart, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa:
Convoy tracking for ADAS on embedded GPUs. Intelligent Vehicles Symposium 2017: 959-965 - [c376]Oliver Reiche, Christof Kobylko, Frank Hannig, Jürgen Teich:
Auto-vectorization for image processing DSLs. LCTES 2017: 21-30 - [c375]Hananeh Aliee, Abbas BanaiyanMofrad, Michael Glaß, Jürgen Teich, Nikil D. Dutt:
Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores. MBMV 2017: 1-12 - [c374]Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich:
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC 2017: 5-12 - [c373]Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich:
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig 2017: 1-3 - [c372]Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig 2017: 1-8 - [c371]Michael Witterauf, Frank Hannig, Jürgen Teich:
Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. RSP 2017: 9-15 - [c370]Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich:
Predictable run-time mapping reconfiguration for real-time applications on many-core systems. RTNS 2017: 148-157 - [c369]Peter Brand, Jonathan Ah Sue, Johannes Brendel, Joachim Falk, Ralph Hasholzner, Jürgen Teich, Stefan Wildermann:
Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems. SCOPES 2017: 64-67 - [c368]Martín Letras, Joachim Falk, Stefan Wildermann, Jürgen Teich:
Automatic Conversion of Simulink Models to SysteMoC Actor Networks. SCOPES 2017: 81-84 - [c367]Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, Stefan Wildermann:
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. SCOPES 2017: 89-92 - [p16]Soonhoi Ha, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer, Shuvra S. Bhattacharyya:
Introduction to Hardware/Software Codesign. Handbook of Hardware/Software Codesign 2017: 3-26 - [p15]Joachim Falk, Christian Haubelt, Jürgen Teich, Christian Zebelein:
SysteMoC: A Data-Flow Programming Language for Codesign. Handbook of Hardware/Software Codesign 2017: 59-97 - [p14]Michael Glaß, Jürgen Teich, Martin Lukasiewycz, Felix Reimann:
Hybrid Optimization Techniques for System-Level Design Space Exploration. Handbook of Hardware/Software Codesign 2017: 217-246 - [e10]Soonhoi Ha, Jürgen Teich:
Handbook of Hardware/Software Codesign. Springer 2017, ISBN 978-94-017-7266-2 [contents] - [i23]Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner:
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning. CoRR abs/1707.08134 (2017) - [i22]Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich:
A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. CoRR abs/1711.05932 (2017) - 2016
- [j72]Luca Fanucci, Jürgen Teich:
Recap of the 2016 DATE Conference & Exhibition. IEEE Des. Test 33(4): 114-117 (2016) - [j71]Emanuele Borgonovo, Hananeh Aliee, Michael Glaß, Jürgen Teich:
A new time-independent reliability importance measure. Eur. J. Oper. Res. 254(2): 427-442 (2016) - [j70]Jürgen Teich:
Invasive computing. it Inf. Technol. 58(6): 263-265 (2016) - [j69]Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau:
Invasive computing for timing-predictable stream processing on MPSoCs. it Inf. Technol. 58(6): 267-280 (2016) - [j68]Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker:
Providing fault tolerance through invasive computing. it Inf. Technol. 58(6): 309-328 (2016) - [j67]Yang Xu, Jürgen Teich:
Hierarchical Statistical Leakage Analysis and Its Application. ACM Trans. Design Autom. Electr. Syst. 21(4): 65:1-65:22 (2016) - [j66]Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
HIPAcc: A Domain-Specific Language and Compiler for Image Processing. IEEE Trans. Parallel Distributed Syst. 27(1): 210-224 (2016) - [j65]Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber:
FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Trans. Reconfigurable Technol. Syst. 9(4): 25:1-25:24 (2016) - [c366]Rafael Rosales, Christian Herglotz, Michael Glaß, André Kaup, Jürgen Teich:
Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-Based Modeling. ARCS 2016: 263-276 - [c365]Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP 2016: 58-66 - [c364]Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich:
Formal reliability analysis of switched ethernet automotive networks under transient transmission errors. DAC 2016: 28:1-28:6 - [c363]Hananeh Aliee, Stefan Vitzethum, Michael Glaß, Jürgen Teich, Emanuele Borgonovo:
Guiding Genetic Algorithms using importance measures for reliable design of embedded systems. DFT 2016: 53-56 - [c362]Zoran A. Salcic, Muhammad Nadeem, HeeJong Park, Jürgen Teich:
A heterogeneous multi-core SoC for mixed criticality industrial automation systems. ETFA 2016: 1-4 - [c361]Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich:
A LUT-Based Approximate Adder. FCCM 2016: 27 - [c360]M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich:
FPGA-based accelerator design from a domain-specific language. FPL 2016: 1-9 - [c359]Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener:
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT 2016: 213-216 - [c358]Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, Jürgen Teich:
Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs. HLDVT 2016: 70-77 - [c357]Bo Wang, Yang Xu, Ralph Hasholzner, Christian Drewes, Rafael Rosales, Sebastian Graf, Joachim Falk, Michael Glaß, Jürgen Teich:
Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design. MBMV 2016: 102-113 - [c356]Zoran A. Salcic, Muhammad Nadeem, HeeJong Park, Jürgen Teich:
Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor. MCSoC 2016: 233-240 - [c355]Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner, Stefan Wildermann:
Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing. MCSoC 2016: 313-320 - [c354]Christian Herglotz, Rafael Rosales, Michael Glaß, Jürgen Teich, André Kaup:
Multi-objective design space exploration for the optimization of the HEVC mode decision process. PCS 2016: 1-5 - [c353]Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, Jürgen Teich:
ActorX10: an actor library for X10. X10@PLDI 2016: 24-29 - [c352]Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann:
Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. ReConFig 2016: 1-7 - [c351]Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich:
ReOrder: Runtime datapath generation for high-throughput multi-stream processing. ReConFig 2016: 1-8 - [c350]Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich:
Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS 2016: 211-218 - [c349]Jonathan Ah Sue, Ralph Hasholzner, Johannes Brendel, Martin Kleinsteuber, Jürgen Teich:
A Binary Time Series Model of LTE Scheduling for Machine Learning Prediction. FAS*W@SASO/ICCAC 2016: 269-270 - [c348]Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix C. Freiling, Michael Glaß, Jürgen Teich:
Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. SCOPES 2016: 153-162 - [p13]Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich:
HIPAcc. FPGAs for Software Programmers 2016: 205-223 - [p12]Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Harald Köstler, Ulrich Rüde, Christian Lengauer:
Systems of Partial Differential Equations in ExaSlang. Software for Exascale Computing 2016: 47-67 - [e9]Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich:
Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings. Lecture Notes in Computer Science 9637, Springer 2016, ISBN 978-3-319-30694-0 [contents] - [e8]Luca Fanucci, Jürgen Teich:
2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016. IEEE 2016, ISBN 978-3-9815-3707-9 [contents] - [i21]Tulika Mitra, Jürgen Teich, Lothar Thiele:
Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441). Dagstuhl Reports 6(10): 120-153 (2016) - 2015
- [j64]Michael Glaß, Hananeh Aliee, Liang Chen, Mojtaba Ebrahimi, Faramarz Khosravi, Veit B. Kleeberger, Alexandra Listl, Daniel Müller-Gritschneder, Fabian Oboril, Ulf Schlichtmann, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis:
Application-aware cross-layer reliability analysis and optimization. it Inf. Technol. 57(3): 159-169 (2015) - [j63]Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer:
Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. 61(10): 615-627 (2015) - [j62]Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich, Dietmar Fey:
Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. 61(10): 646-658 (2015) - [j61]Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. 61(10): 668-680 (2015) - [j60]Joachim Falk, Tobias Schwarzer, Liyuan Zhang, Michael Glaß, Jürgen Teich:
Automatic communication-driven virtual prototyping and design for networked embedded systems. Microprocess. Microsystems 39(8): 1012-1028 (2015) - [c347]Robért Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, Albert Heuberger:
Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. AHS 2015: 1-8 - [c346]Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klopfer, Jürgen Teich, Thomas Wild, Andreas Herkersdorf, Jürgen Becker:
Fault-tolerant communication in invasive networks on chip. AHS 2015: 1-8 - [c345]Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer:
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS 2015: 1-8 - [c344]Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting:
Adaptive fault tolerance through invasive computing. AHS 2015: 1-8 - [c343]Aurang Zaib, Jan Heißwolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf:
Network Interface with Task Spawning Support for NoC-Based DSM Architectures. ARCS 2015: 186-198 - [c342]Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich:
Loop coarsening in C-based High-Level Synthesis. ASAP 2015: 166-173 - [c341]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari:
On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP 2015: 194-201 - [c340]Sebastian Graf, Sebastian Reinhart, Michael Glaß, Jürgen Teich, Daniel Platte:
Robust design of E/E architecture component platforms. DAC 2015: 18:1-18:6 - [c339]Sascha Roloff, David Schafhauser, Frank Hannig, Jürgen Teich:
Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. DAC 2015: 44:1-44:6 - [c338]Jan R. Seyler, Thilo Streichert, Michael Glaß, Nicolas Navet, Jürgen Teich:
Formal analysis of the startup delay of SOME/IP service discovery. DATE 2015: 49-54 - [c337]Faramarz Khosravi, Malte Müller, Michael Glaß, Jürgen Teich:
Uncertainty-aware reliability analysis and optimization. DATE 2015: 97-102 - [c336]Joachim Falk, Tobias Schwarzer, Michael Glaß, Jürgen Teich, Christian Zebelein, Christian Haubelt:
Quasi-static scheduling of data flow graphs in the presence of limited channel capacities. ESTIMedia 2015: 1-10 - [c335]Sascha Roloff, Stefan Wildermann, Frank Hannig, Jürgen Teich:
Invasive computing for predictable stream processing: a simulation-based case study. ESTIMedia 2015: 1-2 - [c334]Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich:
A co-design approach for accelerated SQL query processing via FPGA-based data filtering. FPT 2015: 192-195 - [c333]Éricles Sousa, Frank Hannig, Jürgen Teich:
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. IESS 2015: 218-229 - [c332]Stefan Wildermann, Andreas Weichslgartner, Jürgen Teich:
Design Methodology and Run-Time Management for Predictable Many-Core Systems. ISORC Workshops 2015: 103-110 - [c331]Sebastian Graf, Michael Glaß, Jürgen Teich:
Symbolic Message Routing for Multi-Objective Optimization of Automotive E/E Architecture Component Platforms. MBMV 2015: 115-124 - [c330]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE 2015: 188-197 - [c329]Jürgen Teich:
Adaptive Isolation for Predictable MPSoC Stream Processing. SCOPES 2015: 2 - [c328]Tobias Schwarzer, Joachim Falk, Michael Glaß, Jürgen Teich, Christian Zebelein, Christian Haubelt:
Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling. SCOPES 2015: 68-75 - [c327]Éricles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann:
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. SCOPES 2015: 121-124 - [i20]Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig, Jürgen Teich, Dietmar Fey:
Automatic Optimization of Hardware Accelerators for Image Processing. CoRR abs/1502.07448 (2015) - 2014
- [j59]Richard Membarth, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich, Markus Stürmer, Harald Köstler:
Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language. J. Parallel Distributed Comput. 74(12): 3191-3201 (2014) - [j58]Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit Kleeberger, Michael A. Kochte, Johannes Maximilian Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich:
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. Microelectron. Reliab. 54(6-7): 1066-1074 (2014) - [j57]Alexander Grebhahn, Sebastian Kuckuk, Christian Schmitt, Harald Köstler, Norbert Siegmund, Sven Apel, Frank Hannig, Jürgen Teich:
Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror. Parallel Process. Lett. 24(3) (2014) - [j56]Vijaykrishnan Narayanan, Jürgen Teich:
Introduction to the Special Issue on Domain-Specific Multicore Computing. ACM Trans. Embed. Comput. Syst. 13(4s): 129:1-129:2 (2014) - [j55]Rafael Rosales, Michael Glaß, Jürgen Teich, Bo Wang, Yang Xu, Ralph Hasholzner:
MAESTRO - Holistic Actor-Oriented Modeling of Nonfunctional Properties and Firmware Behavior for MPSoCs. ACM Trans. Design Autom. Electr. Syst. 19(3): 23:1-23:26 (2014) - [j54]Srinivas Boppu, Frank Hannig, Jürgen Teich:
Compact Code Generation for Tightly-Coupled Processor Arrays. J. Signal Process. Syst. 77(1-2): 5-29 (2014) - [j53]Jürgen Teich, Alexandru Tanase, Frank Hannig:
Symbolic Mapping of Loop Programs onto Processor Arrays. J. Signal Process. Syst. 77(1-2): 31-59 (2014) - [c326]Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich:
Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. ACSSC 2014: 398-403 - [c325]Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. ARCS Workshops 2014: 1-8 - [c324]Sascha Roloff, Frank Hannig, Jürgen Teich:
Towards Actor-oriented Programming on PGAS-based Multicore Architectures. ARCS Workshops 2014: 1-2 - [c323]Rafael Rosales, Michael Glaß, Jürgen Teich:
Mahler: Sketch-Based Model-Driven Virtual Prototyping. ARCS 2014: 85-97 - [c322]Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal:
Domain-specific augmentations for High-Level Synthesis. ASAP 2014: 173-177 - [c321]Deepak Gangadharan, Jürgen Teich, Samarjit Chakraborty:
Quality-aware video decoding on thermally-constrained MPSoC platforms. ASAP 2014: 256-263 - [c320]Sebastian Graf, Felix Reimann, Michael Glaß, Jürgen Teich:
Towards scalable symbolic routing for multi-objective networked embedded system design and optimization. CODES+ISSS 2014: 2:1-2:10 - [c319]Hananeh Aliee, Michael Glaß, Faramarz Khosravi, Jürgen Teich:
An efficient technique for computing importance measures in automatic design of dependable embedded systems. CODES+ISSS 2014: 3:1-3:10 - [c318]Oliver Reiche, Moritz Schmid, Frank Hannig, Richard Membarth, Jürgen Teich:
Code generation from a domain-specific language for C-based HLS of hardware accelerators. CODES+ISSS 2014: 17:1-17:10 - [c317]Andreas Weichslgartner, Deepak Gangadharan, Stefan Wildermann, Michael Glaß, Jürgen Teich:
DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems. CODES+ISSS 2014: 34:1-34:10 - [c316]Faramarz Khosravi, Felix Reimann, Michael Glaß, Jürgen Teich:
Multi-Objective Local-Search Optimization using Reliability Importance Measuring. DAC 2014: 15:1-15:6 - [c315]Felix Reimann, Michael Glaß, Jürgen Teich, Alejandro Cook, Laura Rodríguez Gómez, Dominik Ull, Hans-Joachim Wunderlich, Piet Engelke, Ulrich Abelein:
Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. DAC 2014: 96:1-96:9 - [c314]Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, Jürgen Becker:
CAP: Communication Aware Programming. DAC 2014: 105:1-105:6 - [c313]Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour:
Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP 2014: 1-8 - [c312]Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Glaß, Felix Reimann, Laura Rodríguez Gómez, Thomas Russ, Jürgen Teich, Dominik Ull, Hans-Joachim Wunderlich:
Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures. DATE 2014: 1-6 - [c311]Sebastian Graf, Michael Glaß, Jürgen Teich, Christoph Lauer:
Multi-variant-based design space exploration for automotive embedded systems. DATE 2014: 1-6 - [c310]Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich:
Code generation for embedded heterogeneous architectures on android. DATE 2014: 1-6 - [c309]Jan R. Seyler, Thilo Streichert, Juri Warkentin, Matthias Spagele, Michael Glaß, Jürgen Teich:
A self-propagating wakeup mechanism for point-to-point networks with partial network support. DATE 2014: 1-6 - [c308]Stefan Wildermann, Michael Glaß, Jürgen Teich:
Multi-objective distributed run-time resource management for many-cores. DATE 2014: 1-6 - [c307]Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich:
Model-based actor multiplexing with application to complex communication protocols. DATE 2014: 1-4 - [c306]Éricles Sousa, Deepak Gangadharan, Frank Hannig, Jürgen Teich:
Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. DSD 2014: 74-81 - [c305]Liyuan Zhang, Joachim Falk, Tobias Schwarzer, Michael Glaß, Jürgen Teich:
Communication-Driven Automatic Virtual Prototyping for Networked Embedded Systems. DSD 2014: 435-442 - [c304]Sebastian Graf, Michael Glaß, Jürgen Teich, Christoph Lauer:
Design Space Exploration for Automotive E/E Architecture Component Platforms. DSD 2014: 651-654 - [c303]Christian Lengauer, Sven Apel, Matthias Bolten, Armin Größlinger, Frank Hannig, Harald Köstler, Ulrich Rüde, Jürgen Teich, Alexander Grebhahn, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt:
ExaStencils: Advanced Stencil-Code Engineering. Euro-Par Workshops (2) 2014: 553-564 - [c302]Robért Glein, Bernhard Schmidt, Florian Rittner, Jürgen Teich, Daniel Ziener:
A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor. FCCM 2014: 251-258 - [c301]Bernhard Schmidt, Daniel Ziener, Jürgen Teich:
An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). FPGA 2014: 257 - [c300]Andreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich:
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. FPL 2014: 1-8 - [c299]Moritz Schmid, Nicolas Apelt, Frank Hannig, Jürgen Teich:
An image processing library for C-based high-level synthesis. FPL 2014: 1-4 - [c298]Christian Schmitt, Sebastian Kuckuk, Harald Köstler, Frank Hannig, Jürgen Teich:
An Evaluation of Domain-Specific Language Technologies for Code Generation. ICCSA (Workshops/Short Papers/Posters) 2014: 18-26 - [c297]Bernhard Schmidt, Daniel Ziener, Jürgen Teich:
Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning. IPDPS Workshops 2014: 299-304 - [c296]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE 2014: 219-228 - [c295]Bo Wang, Yang Xu, Ralph Hasholzner, Rafael Rosales, Michael Glaß, Jürgen Teich:
End-to-end power estimation for heterogeneous cellular LTE SoCs in early design phases. PATMOS 2014: 1-8 - [c294]Yang Xu, Bo Wang, Jürgen Teich:
Parametric yield optimization using leakage-yield-driven floorplanning. PATMOS 2014: 1-6 - [c293]Stefan Wildermann, Jürgen Teich:
Self-Integration for Virtualization of Embedded Many-Core Systems. SASO Workshops 2014: 170-177 - [c292]Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Harald Köstler, Jürgen Teich:
ExaSlang: a domain-specific language for highly scalable multigrid solvers. WOLFHPC@SC 2014: 42-51 - [c291]Jan R. Seyler, Shurat Rahimov, Thilo Streichert, Michael Glaß, Jürgen Teich:
DPSK modulated wakeup mechanism for point-to-point networks with partial network support. SIES 2014: 238-243 - [p11]Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Samarjit Chakraborty:
Exploration of Distributed Automotive Systems Using Compositional Timing Analysis. Embedded Systems Development, From Functional Models to Implementations 2014: 189-204 - [p10]Michael Glaß, Sebastian Graf, Felix Reimann, Jürgen Teich:
Design and Evaluation of Future Ethernet AVB-Based ECU Networks. Embedded Systems Development, From Functional Models to Implementations 2014: 205-220 - [i19]Frank Hannig, Jürgen Teich:
Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014). CoRR abs/1405.2281 (2014) - [i18]Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Massively Parallel Processor Architectures for Resource-aware Computing. CoRR abs/1405.2907 (2014) - [i17]Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Ulrich Rüde:
A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms. CoRR abs/1406.5369 (2014) - [i16]Moritz Schmid, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich:
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs. CoRR abs/1408.4721 (2014) - 2013
- [j52]Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich:
Symbolic system-level design methodology for multi-mode reconfigurable systems. Des. Autom. Embed. Syst. 17(2): 343-375 (2013) - [j51]Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich:
A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs. ACM Trans. Embed. Comput. Syst. 12(3): 74:1-74:31 (2013) - [j50]Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
Virtual networks - distributed communication resource management. ACM Trans. Reconfigurable Technol. Syst. 6(2): 8:1-8:14 (2013) - [c290]Yang Xu, Bo Wang, Rafael Rosales, Ralph Hasholzner, Jürgen Teich:
On Confident Task-Accurate Performance Estimation. ARCS 2013: 25-37 - [c289]Tobias Ziermann, Zoran Salcic, Jürgen Teich:
HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN). ARCS 2013: 159-170 - [c288]Jürgen Teich, Alexandru Tanase, Frank Hannig:
Symbolic parallelization of loop programs for massively parallel processor arrays. ASAP 2013: 1-9 - [c287]Srinivas Boppu, Frank Hannig, Jürgen Teich:
Loop program mapping and compact code generation for programmable hardware accelerators. ASAP 2013: 10-17 - [c286]Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich:
System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers 2013: 2:1-2:4 - [c285]Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Jürgen Teich:
Run-time adaption for highly-complex multi-core systems. CODES+ISSS 2013: 13:1-13:8 - [c284]Sebastian Graf, Michael Glaß, Dominic Wintermann, Jürgen Teich, Christoph Lauer:
IVaM: Implicit variant modeling and management for automotive embedded systems. CODES+ISSS 2013: 24:1-24:10 - [c283]Yang Xu, Bo Wang, Ralph Hasholzner, Rafael Rosales, Jürgen Teich:
On robust task-accurate performance estimation. DAC 2013: 171:1-171:6 - [c282]Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays. DASIP 2013: 88-95 - [c281]Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
A prototype of an adaptive computer vision algorithm on MPSoC architecture. DASIP 2013: 353-354 - [c280]Stefan Wildermann, Tobias Ziermann, Jürgen Teich:
Game-theoretic analysis of decentralized core allocation schemes on many-core systems. DATE 2013: 1498-1503 - [c279]Hananeh Aliee, Michael Glaß, Felix Reimann, Jürgen Teich:
Automatic success tree-based reliability analysis for the consideration of transient and permanent faults. DATE 2013: 1621-1626 - [c278]Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf:
AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. DSD 2013: 761-768 - [c277]Felix Reimann, Sebastian Graf, Fabian Streit, Michael Glaß, Jürgen Teich:
Timing analysis of Ethernet AVB-based automotive E/E architectures. ETFA 2013: 1-8 - [c276]Christopher Dennl, Daniel Ziener, Jürgen Teich:
Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration. FCCM 2013: 25-28 - [c275]Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich:
Representing mapping and scheduling decisions within dataflow graphs. FDL 2013: 1-8 - [c274]Liyuan Zhang, Michael Glaß, Nils Ballmann, Jürgen Teich:
Bridging algorithm and ESL design: Matlab/Simulink model transformation and validation. FDL 2013: 1-8 - [c273]Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, Thomas Wild, Andreas Herkersdorf, Jürgen Teich, Jürgen Becker:
Hardware Supported Adaptive Data Collection for Networks on Chip. IPDPS Workshops 2013: 153-162 - [c272]Christian Zebelein, Christian Haubelt, Joachim Falk, Jürgen Teich:
Model-Based Representation of Schedules for Dataflow Graphs. MBMV 2013: 105-115 - [c271]Sebastian Graf, Michael Glaß, Jürgen Teich:
Investigating the Impact of Energy-Efficient Ethernet on Automotive Applications via High-level Modeling. MBMV 2013: 117-128 - [c270]Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich:
Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. PARCO 2013: 53-62 - [c269]Moritz Schmid, Frank Hannig, Alexandru Tanase, Jürgen Teich:
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. PARCO 2013: 497-506 - [c268]Moritz Schmid, Markus Blocherer, Frank Hannig, Jürgen Teich:
Real-timerange image preprocessing on FPGAs. ReConFig 2013: 1-8 - [c267]Sascha Roloff, Andreas Weichslgartner, Jan Heißwolf, Frank Hannig, Jürgen Teich:
NoC simulation in heterogeneous architectures for PGAS programming model. M-SCOPES 2013: 77-85 - [p9]Joachim Falk, Christian Haubelt, Christian Zebelein, Jürgen Teich:
Integrated Modeling Using Finite State Machines and Dataflow Graphs. Handbook of Signal Processing Systems 2013: 975-1013 - [i15]Jürgen Teich, Wolfgang Schröder-Preikschat, Andreas Herkersdorf:
Invasive Computing - Common Terms and Granularity of Invasion. CoRR abs/1304.6067 (2013) - 2012
- [j49]Tobias Ziermann, Stefan Wildermann, Nina Mühleis, Jürgen Teich:
Distributed self-organizing bandwidth allocation for priority-based bus communication. Concurr. Comput. Pract. Exp. 24(16): 1903-1917 (2012) - [j48]Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich:
Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. 2012: 608312:1-608312:12 (2012) - [j47]Jürgen Teich:
Hardware/Software Codesign: The Past, the Present, and Predicting the Future. Proc. IEEE 100(Centennial-Issue): 1411-1430 (2012) - [j46]Jens Gladigau, Christian Haubelt, Jürgen Teich:
Model-Based Virtual Prototype Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1572-1585 (2012) - [j45]Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich:
Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. 18(1): 2:1-2:25 (2012) - [j44]Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich:
Dynamic Defragmentation of Reconfigurable Devices. ACM Trans. Reconfigurable Technol. Syst. 5(2): 8:1-8:20 (2012) - [c266]Jürgen Teich:
Keynote address II: Exploiting dynamic hardware reconfigurability for efficiency, performance, and reliability. AHS 2012 - [c265]Yang Xu, Rafael Rosales, Bo Wang, Martin Streubühr, Ralph Hasholzner, Christian Haubelt, Jürgen Teich:
A Very Fast and Quasi-accurate Power-State-Based System-Level Power Modeling Methodology. ARCS 2012: 37-49 - [c264]Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging. ARCS 2012: 147-159 - [c263]Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele:
Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops 2012: 297-319 - [c262]Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich:
Design of Low Power On-chip Processor Arrays. ASAP 2012: 165-168 - [c261]Sascha Roloff, Frank Hannig, Jürgen Teich:
Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. ASP-DAC 2012: 187-192 - [c260]Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt:
FlexRay Static Segment Scheduling. Advances in Real-Time Systems 2012: 323-339 - [c259]Michael Eberl, Michael Glaß, Jürgen Teich, Ulrich Abelein:
Considering diagnosis functionality during automatic system-level design of automotive networks. DAC 2012: 205-213 - [c258]Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich:
A prototype of an invasive tightly-coupled processor array. DASIP 2012: 1-2 - [c257]Paul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich:
Designing FlexRay-based automotive architectures: A holistic OEM approach. DATE 2012: 276-279 - [c256]Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich:
Variation-aware leakage power model extraction for system-level hierarchical power analysis. DATE 2012: 346-351 - [c255]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
Mastering Software Variant Explosion for GPU Accelerators. Euro-Par Workshops 2012: 123-132 - [c254]Christopher Dennl, Daniel Ziener, Jürgen Teich:
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. FCCM 2012: 45-52 - [c253]Moritz Schmid, Frank Hannig, Jürgen Teich:
Power Management Strategies for Serial RapidIO Endpoints in FPGAs. FCCM 2012: 101-108 - [c252]Jürgen Teich, Andreas Weichslgartner, Benjamin Oechslein, Wolfgang Schröder-Preikschat:
Invasive computing - Concepts and overheads. FDL 2012: 217-224 - [c251]Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IPDPS Workshops 2012: 234-241 - [c250]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
Generating Device-specific GPU Code for Local Operators in Medical Imaging. IPDPS 2012: 569-581 - [c249]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging. ISPDC 2012: 211-218 - [c248]Sebastian Graf, Michael Glaß, Jürgen Teich:
Unreliable Data Transmissions und Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes. MBMV 2012: 13-24 - [c247]Christian Zebelein, Christian Haubelt, Joachim Falk, Jürgen Teich:
Exploiting Model-Knowledge in High-Level Synthesis. MBMV 2012: 181-191 - [c246]Liyuan Zhang, Michael Glaß, Martin Streubühr, Jürgen Teich, Andreas von Schwerin, Kai Liu:
Actor-oriented Modeling und Simulation of Cut-through Communication in Network Controllers. MBMV 2012: 193-204 - [c245]Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener:
FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). ReConFig 2012: 1-6 - [c244]Michael Glaß, Heng Yu, Felix Reimann, Jürgen Teich:
Cross-Level Compositional Reliability Analysis for Embedded Systems. SAFECOMP 2012: 111-124 - [c243]Rainer Kiesel, Martin Streubühr, Christian Haubelt, Anestis Terzis, Jürgen Teich:
Virtual prototyping for efficient multi-core ECU development of driver assistance systems. ICSAMOS 2012: 33-40 - [c242]Michael Glaß, Jürgen Teich, Liyuan Zhang:
A co-simulation approach for system-level analysis of embedded control systems. ICSAMOS 2012: 355-362 - [c241]Richard Membarth, Frank Hannig, Jürgen Teich, Harald Köstler:
Towards Domain-Specific Computing for Stencil Codes in HPC. SC Companion 2012: 1133-1138 - [c240]Sascha Roloff, Frank Hannig, Jürgen Teich:
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation. Map2MPSoC/SCOPES 2012: 52-61 - 2011
- [b5]Joachim Keinert, Jürgen Teich:
Design of Image Processing Embedded Systems Using Multidimensional Data Flow. Embedded Systems, Springer 2011, ISBN 978-1-4419-7181-4 - [j43]Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich:
Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. IEEE Embed. Syst. Lett. 3(2): 58-61 (2011) - [j42]Dmitrij Kissler, Frank Hannig, Jürgen Teich:
Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electron. 7(1): 29-40 (2011) - [j41]Nina Mühleis, Michael Glaß, Liyuan Zhang, Jürgen Teich:
A co-simulation approach for control performance analysis during design space exploration of cyber-physical systems. SIGBED Rev. 8(2): 23-26 (2011) - [c239]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration. ARCS 2011: 62-73 - [c238]Andreas Kern, Dominik Reinhard, Thilo Streichert, Jürgen Teich:
Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa. ARCS 2011: 259-270 - [c237]Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich:
Decentralized dynamic resource management support for massively parallel processor arrays. ASAP 2011: 87-94 - [c236]Tobias Ziermann, Zoran Salcic, Jürgen Teich:
Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems. ATC 2011: 132-148 - [c235]Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich:
Design and architectures for dependable embedded systems. CODES+ISSS 2011: 69-78 - [c234]Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang:
Mapping of applications to MPSoCs. CODES+ISSS 2011: 109-118 - [c233]Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich:
Symbolic design space exploration for multi-mode reconfigurable systems. CODES+ISSS 2011: 129-138 - [c232]Felix Reimann, Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich:
Symbolic system synthesis in the presence of stringent real-time constraints. DAC 2011: 393-398 - [c231]Andreas Kern, Helge Zinner, Thilo Streichert, Josef Nöbauer, Jürgen Teich:
Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networks. DAC 2011: 597-602 - [c230]Andreas Kern, Thilo Streichert, Jürgen Teich:
An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP). DATE 2011: 112-117 - [c229]Tobias Ziermann, Jürgen Teich, Zoran Salcic:
DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systems. DATE 2011: 269-272 - [c228]Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich:
A rule-based static dataflow clustering algorithm for efficient embedded software synthesis. DATE 2011: 521-526 - [c227]Martin Streubühr, Rafael Rosales, Ralph Hasholzner, Christian Haubelt, Jürgen Teich:
ESL power and performance estimation for heterogeneous MPSOCS using SystemC. FDL 2011: 1-8 - [c226]Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich:
Stress-Aware Module Placement on Reconfigurable Devices. FPL 2011: 277-281 - [c225]Stefan Wildermann, Jürgen Teich, Daniel Ziener:
Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. FPL 2011: 429-434 - [c224]Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich:
Runtime stress-aware replica placement on reconfigurable devices under safety constraints. FPT 2011: 1-6 - [c223]Stefan Wildermann, Felix Reimann, Jürgen Teich, Zoran Salcic:
Operational mode exploration for reconfigurable systems with multiple applications. FPT 2011: 1-8 - [c222]Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich:
An FPGA implementation of a threat-based strategy for Connect6. FPT 2011: 1-4 - [c221]Martin Lukasiewycz, Michael Glaß, Felix Reimann, Jürgen Teich:
Opt4J: a modular framework for meta-heuristic optimization. GECCO 2011: 1723-1730 - [c220]Josef Angermeier, Eugen Sibirko, Rolf Wanka, Jürgen Teich:
Bitonic Sorting on Dynamically Reconfigurable Architectures. IPDPS Workshops 2011: 314-317 - [c219]Vahid Lari, Frank Hannig, Jürgen Teich:
Distributed Resource Reservation in Massively Parallel Processor Arrays. IPDPS Workshops 2011: 318-321 - [c218]Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, Jürgen Teich:
Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor. MARC Symposium 2011: 111-114 - [c217]Richard Membarth, Frank Hannig, Jürgen Teich, Gerhard Litz, Heinz Hornegger:
Detector defect correction of medical images on graphics processors. Image Processing 2011: 79624M - [c216]Andreas Weichslgartner, Stefan Wildermann, Jürgen Teich:
Dynamic decentralized mapping of tree-structured applications on NoC architectures. NOCS 2011: 201-208 - [c215]Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade:
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig 2011: 392-397 - [c214]Philipp Kutzer, Jens Gladigau, Christian Haubelt, Jürgen Teich:
Automatic generation of system-level virtual prototypes from streaming application models. International Symposium on Rapid System Prototyping 2011: 128-134 - [c213]Rainer Kiesel, Martin Streubühr, Christian Haubelt, Otto Löhlein, Jürgen Teich:
Calibration and validation of software performance models for pedestrian detection systems. ICSAMOS 2011: 182-189 - [c212]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration. SASP 2011: 78-81 - [c211]Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich, Andreas Zwinkau:
Resource-aware programming and simulation of MPSoC architectures through extension of X10. SCOPES 2011: 48-55 - [c210]Andreas Kern, Hongyan Zhang, Thilo Streichert, Jürgen Teich:
Testing switched Ethernet networks in automotive embedded systems. SIES 2011: 150-155 - [p8]Tobias Ziermann, Stefan Wildermann, Jürgen Teich:
OrganicBus: Organic Self-organising Bus-Based Communication Systems. Organic Computing 2011: 489-501 - [p7]Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat, Gregor Snelting:
Invasive Computing: An Overview. Multiprocessor System-on-Chip 2011: 241-268 - 2010
- [b4]Christian Haubelt, Jürgen Teich:
Digitale Hardware/Software-Systeme: Spezifikation und Verifikation. eXamen.press, Springer 2010, ISBN 978-3-642-05355-9 - [j40]Udo Kebschull, Marco Platzner, Jürgen Teich:
Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial]. IET Comput. Digit. Tech. 4(3): 157-158 (2010) - [j39]Joachim Falk, Christian Zebelein, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya:
Analysis of SystemC actor networks for efficient synthesis. ACM Trans. Embed. Comput. Syst. 10(2): 18:1-18:34 (2010) - [c209]Stefan Wildermann, Andreas Oetken, Jürgen Teich, Zoran A. Salcic:
Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras. ATC 2010: 1-16 - [c208]Felix Reimann, Michael Glaß, Christian Haubelt, Michael Eberl, Jürgen Teich:
Improving platform-based system synthesis by satisfiability modulo theories solving. CODES+ISSS 2010: 135-144 - [c207]Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich:
Towards scalable system-level reliability analysis. DAC 2010: 234-239 - [c206]Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich:
A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE 2010: 375-380 - [c205]Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch:
Efficient High-Level modeling in the networking domain. DATE 2010: 1189-1194 - [c204]Martin Lukasiewycz, Michael Glaß, Jürgen Teich:
Robust design of embedded systems. DATE 2010: 1578-1583 - [c203]Samarjit Chakraborty, S. Ramesh, Jürgen Teich:
Model-based analysis, synthesis and testing of automotive hardware/software architectures. EMSOFT 2010: 299-300 - [c202]Richard Membarth, Anton Lokhmotov, Jürgen Teich:
Generating GPU Code from a High-Level Representation for Image Processing Kernels. Euro-Par Workshops (1) 2010: 270-280 - [c201]Joon Edward Sim, Weng-Fai Wong, Gregor Walla, Tobias Ziermann, Jürgen Teich:
Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems. FCCM 2010: 179-182 - [c200]Daniel Ziener, Florian Baueregger, Jürgen Teich:
Using the Power Side Channel of FPGAs for Communication. FCCM 2010: 237-244 - [c199]Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch:
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. FPL 2010: 234-239 - [c198]Frank Hannig, Moritz Schmid, Jürgen Teich, Heinz Hornegger:
A deeply pipelined and parallel architecture for denoising medical images. FPT 2010: 485-490 - [c197]Daniel Ziener, Florian Baueregger, Jürgen Teich:
Multiplexing Methods for Power Watermarking. HOST 2010: 36-41 - [c196]Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich:
Symbolic system level reliability analysis. ICCAD 2010: 185-189 - [c195]Andreas Kern, Christoph Schmutzler, Thilo Streichert, Michael Hübner, Jürgen Teich:
Network Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded Systems. ICCCN 2010: 1-6 - [c194]Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich:
Virtual area management: Multitasking on dynamically partially reconfigurable devices. IPDPS Workshops 2010: 1-4 - [c193]Tobias Ziermann, Jürgen Teich:
Adaptive traffic scheduling techniques for mixed real-time and streaming applications on reconfigurable hardware. IPDPS Workshops 2010: 1-4 - [c192]Tobias Ziermann, Nina Mühleis, Stefan Wildermann, Jürgen Teich:
A Self-Organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-Based Bus Communication. ISORC Workshops 2010: 11-20 - [c191]Rainer Kiesel, Otto Löhlein, Anestis Terzis, Martin Streubühr, Christian Haubelt, Jürgen Teich:
Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation. MBMV 2010: 117-126 - [c190]Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich, Rainer Dorsch:
Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models. MBMV 2010: 137-146 - [c189]Josef Angermeier, Stefan Wildermann, Eugen Sibirko, Jürgen Teich:
Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures. ReConFig 2010: 91-96 - [c188]Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich:
A system-level synthesis approach from formal application models to generic bus-based MPSoCs. ICSAMOS 2010: 118-125 - [p6]Joachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Christian Zebelein:
Integrated Modeling using Finite State Machines and Dataflow Graphs. Handbook of Signal Processing Systems 2010: 1041-1075 - [p5]Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich:
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform. Dynamically Reconfigurable Systems 2010: 51-71 - [p4]Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen:
ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices. Dynamically Reconfigurable Systems 2010: 199-221 - [p3]Christian Haubelt, Dirk Koch, Felix Reimann, Thilo Streichert, Jürgen Teich:
ReCoNets - Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections. Dynamically Reconfigurable Systems 2010: 223-243 - [e7]Marco Platzner, Jürgen Teich, Norbert Wehn:
Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications. Springer 2010, ISBN 978-9-04-813484-7 [contents] - [e6]François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski:
21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010. IEEE Computer Society 2010, ISBN 978-1-4244-6967-3 [contents] - [e5]Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede:
Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010. Dagstuhl Seminar Proceedings 10281, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany 2010 [contents] - [i14]Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede:
10281 Abstracts Collection - Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2010 - [i13]Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede:
10281 Summary - Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2010 - [i12]Daniel Ziener, Jürgen Teich:
New Directions for IP Core Watermarking and Identification. Dynamically Reconfigurable Architectures 2010 - [i11]Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich:
Maintaining Virtual Areas on FPGAs using Strip Packing with Delays. CoRR abs/1001.4493 (2010) - [i10]Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich:
No-Break Dynamic Defragmentation of Reconfigurable. CoRR abs/1012.5330 (2010)
2000 – 2009
- 2009
- [j38]Nikil D. Dutt, Jürgen Teich:
CODES+ISSS 2007 guest editors' introduction. Des. Autom. Embed. Syst. 13(1-2): 51-52 (2009) - [j37]Daniel Ziener, Jürgen Teich:
Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. Int. J. Auton. Adapt. Commun. Syst. 2(3): 256-275 (2009) - [j36]Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich:
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. J. Low Power Electron. 5(1): 96-105 (2009) - [j35]Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier:
A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems 33(1): 53-62 (2009) - [j34]Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor P. Stefanov, Daniel D. Gajski, Jürgen Teich:
Electronic System-Level Synthesis Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1517-1530 (2009) - [j33]Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith:
SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. ACM Trans. Design Autom. Electr. Syst. 14(1): 1:1-1:23 (2009) - [j32]Dirk Koch, Christian Beckhoff, Jürgen Teich:
Hardware Decompression Techniques for FPGA-Based Embedded Systems. ACM Trans. Reconfigurable Technol. Syst. 2(2): 9:1-9:23 (2009) - [c187]Frank Hannig, Hritam Dutta, Jürgen Teich:
Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS 2009: 16-27 - [c186]Hritam Dutta, Frank Hannig, Jürgen Teich:
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS 2009: 233-245 - [c185]Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich:
Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP 2009: 161-168 - [c184]Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich:
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP 2009: 211-214 - [c183]Martin Lukasiewycz, Michael Glaß, Jürgen Teich:
Exploiting data-redundancy in reliability-aware networked embedded system design. CODES+ISSS 2009: 229-238 - [c182]Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt:
FlexRay schedule optimization of the static segment. CODES+ISSS 2009: 363-372 - [c181]Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty:
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. DAC 2009: 43-46 - [c180]Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich:
Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE 2009: 135-140 - [c179]Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich:
Incorporating graceful degradation into embedded system design. DATE 2009: 320-323 - [c178]Martin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich:
Combined system synthesis and communication architecture exploration for MPSoCs. DATE 2009: 472-477 - [c177]Tobias Ziermann, Stefan Wildermann, Jürgen Teich:
CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. DATE 2009: 1088-1093 - [c176]Dirk Koch, Christian Beckhoff, Jürgen Teich:
Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems. FCCM 2009: 251-254 - [c175]Joon Edward Sim, Weng-Fai Wong, Jürgen Teich:
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators. FCCM 2009: 279-282 - [c174]Martin Streubühr, Jens Gladigau, Christian Haubelt, Jürgen Teich:
Efficient approximately-timed performance modeling for architectural exploration of MPSoCs. FDL 2009: 1-6 - [c173]Dirk Koch, Christian Beckhoff, Jürgen Teich:
A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. FPGA 2009: 253-256 - [c172]Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich:
Self-organizing multi-cue fusion for FPGA-based embedded imaging. FPL 2009: 132-137 - [c171]Josef Angermeier, Abdulazim Amouri, Jürgen Teich:
General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems. FPL 2009: 302-307 - [c170]Jürgen Teich:
From dynamic reconfiguration to self-reconfiguration: Invasive algorithms and architectures. FPT 2009: 11-12 - [c169]Abdulazim Amouri, Farhadur Arifin, Frank Hannig, Jürgen Teich:
FPGA implementation of an invasive computing architecture. FPT 2009: 135-142 - [c168]Vahid Lari, Frank Hannig, Jürgen Teich:
System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. ICPP Workshops 2009: 528-534 - [c167]Jens Gladigau, Christian Haubelt, Martin Streubühr, Jürgen Teich, Axel Schneider, Joachim Knäblein, Michael Lindig:
Testfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen. MBMV 2009: 157-166 - [c166]Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich:
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS 2009: 277-288 - [c165]Stefan Wildermann, Tobias Ziermann, Jürgen Teich:
Self-organizing Bandwidth Sharing in Priority-Based Medium Access. SASO 2009: 144-153 - 2008
- [j31]Jürgen Teich:
Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen). it Inf. Technol. 50(5): 300-310 (2008) - [j30]Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich:
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1210-1219 (2008) - [j29]Daniel Ziener, Jürgen Teich:
Power Signature Watermarking of IP Cores for FPGAs. J. Signal Process. Syst. 51(1): 123-136 (2008) - [c164]Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele:
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC 2008: 148-158 - [c163]Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich:
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289 - [c162]Thilo Streichert, Michael Glaß, Rolf Wanka, Christian Haubelt, Jürgen Teich:
Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks. ARCS 2008: 23-37 - [c161]Robert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich:
Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. ARCS 2008: 117-129 - [c160]Joachim Keinert, Christian Haubelt, Jürgen Teich:
Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication. ARCS 2008: 130-143 - [c159]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich:
Efficient symbolic multi-objective design space exploration. ASP-DAC 2008: 691-696 - [c158]Daniel Ziener, Jürgen Teich:
Concepts for Autonomous Control Flow Checking for Embedded CPUs. ATC 2008: 234-248 - [c157]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich:
A feasibility-preserving local search operator for constrained discrete optimization problems. IEEE Congress on Evolutionary Computation 2008: 1968-1975 - [c156]Felix Reimann, Michael Glaß, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich:
Symbolic voter placement for dependability-aware system synthesis. CODES+ISSS 2008: 237-242 - [c155]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Richard Regler, Bardo Lang:
Concurrent topology and routing optimization in automotive network integration. DAC 2008: 626-629 - [c154]Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich:
Symbolic Reliability Analysis and Optimization of ECU Networks. DATE 2008: 158-163 - [c153]Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig:
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. DSD 2008: 345-352 - [c152]Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich:
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD 2008: 391-398 - [c151]Joachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya:
A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications. EMSOFT 2008: 189-198 - [c150]Dirk Koch, Christian Haubelt, Jürgen Teich:
Efficient Reconfigurable On-Chip Buses for FPGAs. FCCM 2008: 287-290 - [c149]Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig:
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM 2008: 306-309 - [c148]Jens Gladigau, Christian Haubelt, Jürgen Teich:
Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models. FDL 2008: 1-6 - [c147]Jens Gladigau, Christian Haubelt, Jürgen Teich:
Symbolic Scheduling of SystemC Dataflow Designs. FDL (Selected Papers) 2008: 183-199 - [c146]Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich:
No-break dynamic defragmentation of reconfigurable devices. FPL 2008: 113-118 - [c145]Dirk Koch, Christian Beckhoff, Jürgen Teich:
ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. FPL 2008: 119-124 - [c144]Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker:
Fine grain reconfigurable architectures. FPL 2008: 348 - [c143]Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
Coarse-grained reconfiguration. FPL 2008: 349 - [c142]Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig:
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL 2008: 391-396 - [c141]Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich:
A comparison of embedded reconfigurable video-processing architectures. FPL 2008: 587-590 - [c140]Moritz Schmid, Daniel Ziener, Jürgen Teich:
Netlist-level IP protection by watermarking for LUT-based FPGAs. FPT 2008: 209-216 - [c139]Stefan Wildermann, Jürgen Teich:
A Sequential Learning Resource Allocation Network for Image Processing Applications. HIS 2008: 132-137 - [c138]Josef Angermeier, Jürgen Teich:
Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads. IPDPS 2008: 1-8 - [c137]Jens Gladigau, Frank Blendinger, Christian Haubelt, Jürgen Teich:
Symbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen. MBMV 2008: 109-118 - [c136]Frank Hannig, Holger Ruckdeschel, Jürgen Teich:
The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications. MBMV 2008: 129-138 - [c135]Martin Streubühr, Michael Jäntsch, Christian Haubelt, Jürgen Teich, Axel Schneider:
Semi-Automatic Generation of mixed Hardware/Software Prototypes from Simulink Models. MBMV 2008: 139-148 - [c134]Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich:
Classification of General Data Flow Actors into Known Models of Computation. MEMOCODE 2008: 119-128 - [c133]Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich:
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS 2008: 307-317 - [c132]Martin Lukasiewycz, Michael Glaß, Jürgen Teich:
A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems. PPSN 2008: 919-928 - [c131]Stefan Wildermann, Jürgen Teich:
3D Person Tracking with a Color-Based Particle Filter. RobVis 2008: 327-340 - [c130]Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich:
Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. IEEE International Workshop on Rapid System Prototyping 2008: 142-148 - [c129]Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich:
Symbolic Reliability Analysis of Self-healing Networked Embedded Systems. SAFECOMP 2008: 139-152 - [c128]Michael Glaß, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich:
Multi-objective routing and topology optimization in networked embedded systems. ICSAMOS 2008: 74-81 - [p2]Thilo Streichert, Christian Haubelt, Dirk Koch, Jürgen Teich:
Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems. Organic Computing 2008: 241-260 - 2007
- [b3]Jürgen Teich, Christian Haubelt:
Digitale Hardware/Software-Systeme: Synthese und Optimierung, 2. Auflage. eXamen.press, Springer 2007, ISBN 978-3-540-46822-6 - [j28]Neil Bergmann, Marco Platzner, Jürgen Teich:
Dynamically Reconfigurable Architectures. EURASIP J. Embed. Syst. 2007 (2007) - [j27]Christian Haubelt, Joachim Falk, Joachim Keinert, Thomas Schlichter, Martin Streubühr, Andreas Deyhle, Andreas Hadert, Jürgen Teich:
A SystemC-Based Design Methodology for Digital Signal Processing Systems. EURASIP J. Embed. Syst. 2007 (2007) - [j26]Jürgen Teich:
Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme). it Inf. Technol. 49(3): 139- (2007) - [j25]Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens). it Inf. Technol. 49(3): 143- (2007) - [j24]Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich:
Efficient control generation for mapping nested loop programs onto processor arrays. J. Syst. Archit. 53(5-6): 300-309 (2007) - [j23]Thilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich:
Design space exploration of reliable networked embedded systems. J. Syst. Archit. 53(10): 751-763 (2007) - [j22]Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda:
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. J. VLSI Signal Process. 47(1): 15-31 (2007) - [c127]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282 - [c126]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich:
SAT-decoding in evolutionary algorithms for discrete constrained optimization problems. IEEE Congress on Evolutionary Computation 2007: 935-942 - [c125]Michael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich:
Interactive presentation: Reliability-aware system synthesis. DATE 2007: 409-414 - [c124]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich:
Symbolic Archive Representation for a Fast Nondominance Test. EMO 2007: 111-125 - [c123]Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet:
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24 - [c122]Joachim Keinert, Joachim Falk, Christian Haubelt, Jürgen Teich:
Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms. ESTIMedia 2007: 113-118 - [c121]Jens Gladigau, Christian Haubelt, Bernhard Niemann, Jürgen Teich:
Mapping Actor-Oriented Models to TLM Architectures. FDL 2007: 128-133 - [c120]Dirk Koch, Christian Haubelt, Jürgen Teich:
Efficient hardware checkpointing: concepts, overhead analysis, and implementation. FPGA 2007: 188-196 - [c119]Dirk Koch, Christian Beckhoff, Jürgen Teich:
Bitstream Decompression for High Speed FPGA Configuration from Slow Memories. FPT 2007: 161-168 - [c118]Dirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich:
Modeling and Synthesis of Hardware-Software Morphing. ISCAS 2007: 2746-2749 - [c117]Martin Streubühr, Carsten Riedel, Christian Haubelt, Jürgen Teich:
System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC. MBMV 2007: 59-68 - [c116]Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68 - [c115]Joachim Keinert, Christian Haubelt, Jürgen Teich:
Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow. ICSAMOS 2007: 161-168 - [c114]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich:
Solving Multi-objective Pseudo-Boolean Problems. SAT 2007: 56-69 - [c113]Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich:
Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80 - [e4]Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich:
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007. ACM 2007, ISBN 978-1-59593-824-4 [contents] - [e3]Christian Haubelt, Jürgen Teich:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7, 2007. Berichte aus der Informatik, Shaker 2007, ISBN 978-3-8322-5956-3 [contents] - 2006
- [j21]Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich:
Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems. EURASIP J. Embed. Syst. 2006 (2006) - [j20]Frank Hannig, Hritam Dutta, Jürgen Teich:
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. Int. J. Embed. Syst. 2(1/2): 114-127 (2006) - [j19]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich:
Higher-Dimensional Packing with Order Constraints. SIAM J. Discret. Math. 20(4): 1056-1078 (2006) - [j18]Jürgen Teich, Shuvra S. Bhattacharyya:
Analysis of Dataflow Programs with Interval-limited Data-rates. J. VLSI Signal Process. 43(2-3): 247-258 (2006) - [c112]Hritam Dutta, Frank Hannig, Jürgen Teich:
Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS 2006: 176-190 - [c111]Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich:
A Flexible Reconfiguration Manager for the Erlangen Slot Machine. ARCS Workshops 2006: 183-194 - [c110]Dirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt, Jürgen Teich:
An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks. ARCS 2006: 202-216 - [c109]Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger:
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340 - [c108]Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich:
A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195 - [c107]Jürgen Teich:
Are current ESL tools meeting the requirements of advanced embedded systems? CODES+ISSS 2006: 166 - [c106]Martin Streubühr, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf:
Task-accurate performance modeling in SystemC for real-time multi-processor architectures. DATE 2006: 480-481 - [c105]Dirk Koch, Matthiaas Koerber, Jürgen Teich:
Searching RC5-Keys with Distributed Reconfigurable Computing. ERSA 2006: 42-48 - [c104]Jürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner:
Topic 18: Embedded Parallel Systems. Euro-Par 2006: 1179 - [c103]Joachim Falk, Christian Haubelt, Jürgen Teich:
Efficient Representation and Simulation of Model-Based Designs. FDL 2006: 129-135 - [c102]Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich:
Minimizing Communication Cost for Reconfigurable Slot Modules. FPL 2006: 1-6 - [c101]Daniel Ziener, Stefan Assmus, Jürgen Teich:
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. FPL 2006: 1-6 - [c100]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
A highly parameterizable parallel processor array architecture. FPT 2006: 105-112 - [c99]Daniel Ziener, Jürgen Teich:
FPGA core watermarking based on power signature analysis. FPT 2006: 205-212 - [c98]Joachim Keinert, Christian Haubelt, Jürgen Teich:
Modeling and Analysis of Windowed Synchronous Algorithms. ICASSP (3) 2006: 892-895 - [c97]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
Hardware Cost Analysis for Weakly Programmable Processor Arrays. SoC 2006: 1-4 - [c96]Thomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich:
Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms. ISVLSI 2006: 309-316 - [c95]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker:
An Architecture Description Language for Massively Parallel Processor Architectures. MBMV 2006: 11-20 - [c94]Hritam Dutta, Frank Hannig, Jürgen Teich:
Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC 2006: 153-160 - [c93]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37 - [c92]Thilo Streichert, Christian Haubelt, Jürgen Teich:
Multi-Objective Topology Optimization for Networked Embedded Systems. ICSAMOS 2006: 93-98 - [c91]Thilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich:
Dynamic task binding for hardware/software reconfigurable networks. SBCCI 2006: 38-43 - [e2]Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich:
Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006. Dagstuhl Seminar Proceedings 06141, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006 [contents] - [i9]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas:
06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006 - [i8]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas:
06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006 - [i7]Diana Göhringer, Mateusz Majer, Jürgen Teich:
Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. Dynamically Reconfigurable Architectures 2006 - 2005
- [j17]Ali Ahmadinia, Christophe Bobda, Jürgen Teich:
Online placement for dynamically reconfigurable devices. Int. J. Embed. Syst. 1(3/4): 165-178 (2005) - [c90]Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich:
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. ASAP 2005: 9-14 - [c89]Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jürgen Teich:
A system-level approach to hardware reconfigurable systems. ASP-DAC 2005: 298-301 - [c88]Thilo Streichert, Christian Haubelt, Jürgen Teich:
Online hardware/software partitioning in networked embedded systems. ASP-DAC 2005: 982-985 - [c87]S. Helwig, Christian Haubelt, Jürgen Teich:
Modeling and analysis of indirect communication in particle swarm optimization. Congress on Evolutionary Computation 2005: 1246-1253 - [c86]Thilo Streichert, Christian Haubelt, Jürgen Teich:
Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks. DATE 2005: 894-895 - [c85]Christian Haubelt, Jürgen Gamenik, Jürgen Teich:
Initial Population Construction for Convergence Improvement of MOEAs. EMO 2005: 191-205 - [c84]Frank Hannig, Jürgen Teich:
Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA 2005: 78-84 - [c83]Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich:
Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104 - [c82]Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. FCCM 2005: 319-320 - [c81]Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. FPL 2005: 153-158 - [c80]Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich:
The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. FPT 2005: 37-42 - [c79]Thomas Schlichter, Christian Haubelt, Jürgen Teich:
Improving EA-based design space exploration by utilizing symbolic feasibility tests. GECCO 2005: 1945-1952 - [c78]Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich, Lothar Thiele:
SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. GI Jahrestagung (2) 2005: 693-697 - [c77]Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich:
Packet Routing in Dynamically Changing Networks on Chip. IPDPS 2005 - [c76]Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34 - [c75]Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. IEEE International Workshop on Rapid System Prototyping 2005: 84-90 - [c74]Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich:
Automatic FIR Filter Generation for FPGAs. SAMOS 2005: 51-61 - [p1]Sanaz Mostaghim, Jürgen Teich:
Quad-trees: A Data Structure for Storing Pareto Sets in Multiobjective Evolutionary Algorithms with Elitism. Evolutionary Multiobjective Optimization 2005: 81-104 - [i6]Sanaz Mostaghim, Jürgen Teich:
A New Approach on Many Objective Diversity Measurement. Practical Approaches to Multi-Objective Optimization 2005 - [i5]Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. CoRR abs/cs/0503066 (2005) - [i4]Jan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich:
Defragmenting the Module Layout of a Partially Reconfigurable Device. CoRR abs/cs/0505005 (2005) - [i3]Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. CoRR abs/cs/0510039 (2005) - 2004
- [j16]Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler:
Systematic integration of parameterized local search into evolutionary algorithms. IEEE Trans. Evol. Comput. 8(2): 137-155 (2004) - [c73]Ali Ahmadinia, Christophe Bobda, Jürgen Teich:
A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware. ARCS 2004: 125-139 - [c72]Christophe Bobda, Ali Ahmadinia, Jürgen Teich:
Generation of Distributed Arithmetic Designs for Reconfigurable Application. ARCS Workshops 2004: 205-214 - [c71]Frank Hannig, Jürgen Teich:
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. ASAP 2004: 17-27 - [c70]Sanaz Mostaghim, Michael Hoffmann, Peter H. Konig, Thomas Frauenheim, Jürgen Teich:
Molecular force field parametrization using multi-objective evolutionary algorithms. IEEE Congress on Evolutionary Computation 2004: 212-219 - [c69]Sanaz Mostaghim, Jürgen Teich:
Covering Pareto-optimal fronts by subswarms in multi-objective particle swarm optimization. IEEE Congress on Evolutionary Computation 2004: 1404-1411 - [c68]Dirk Koch, Jürgen Teich:
Platform-independent methodology for partial reconfiguration. Conf. Computing Frontiers 2004: 398-403 - [c67]Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen:
Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. FPL 2004: 847-851 - [c66]Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich:
A Dynamic NoC Approach for Communication in Reconfigurable Devices. FPL 2004: 1032-1036 - [c65]Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler:
Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms. GECCO (2) 2004: 383-384 - [c64]Frank Hannig, Hritam Dutta, Jürgen Teich:
Regular mapping for coarse-grained reconfigurable architectures. ICASSP (5) 2004: 57-60 - [c63]Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich:
A New Approach for On-line Placement on Reconfigurable Devices. IPDPS 2004 - [c62]Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich:
Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. IPDPS 2004 - [c61]Frank Hannig, Hritam Dutta, Jürgen Teich:
Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS 2004 - [c60]Frank Hannig, Jürgen Teich:
Dynamic Piecewise Linear/Regular Algorithms. PARELEC 2004: 79-84 - [c59]Christian Haubelt, Dirk Koch, Jürgen Teich:
Basic OS Support for Distributed Reconfigurable Hardware. SAMOS 2004: 30-38 - [c58]Jürgen Teich, Shuvra S. Bhattacharyya:
Analysis of Dataflow Programs with Interval-Limited Data-Rates. SAMOS 2004: 507-518 - [c57]Alexey Kupriyanov, Frank Hannig, Jürgen Teich:
High-Speed Event-Driven RTL Compiled Simulation. SAMOS 2004: 519-529 - [c56]Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich:
Task scheduling for heterogeneous reconfigurable computers. SBCCI 2004: 22-27 - [i2]Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen:
Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. CoRR cs.DS/0406035 (2004) - 2003
- [j15]Marcus Bednara, Klaus Danne, Markus Deppe, Oliver Oberschelp, Frank Slomka, Jürgen Teich:
Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware. EURASIP J. Adv. Signal Process. 2003(6): 594-602 (2003) - [j14]Dirk Fischer, Jürgen Teich, Ralph Weper, Michael Thies:
BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs. J. Circuits Syst. Comput. 12(3): 353- (2003) - [j13]Marcus Bednara, Jürgen Teich:
Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. J. Supercomput. 26(2): 149-165 (2003) - [c55]Christian Haubelt, Jürgen Teich:
Accelerating design space exploration using pareto-front arithmetics. ASP-DAC 2003: 525-531 - [c54]Christian Reinhold, P. Kralicek, Werner John, Jürgen Teich:
Synthesizing passive networks by applying genetic programming and evolution strategies. IEEE Congress on Evolutionary Computation 2003: 1740-1747 - [c53]Sanaz Mostaghim, Jürgen Teich:
The role of ε-dominance in multi objective particle swarm optimization methods. IEEE Congress on Evolutionary Computation 2003: 1764-1771 - [c52]Jens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich:
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. DATE 2003: 11110-11111 - [c51]Christian Haubelt, Jürgen Teich, Rainer Feldmann, Burkhard Monien:
SAT-Based Techniques in System Synthesis. DATE 2003: 11168-11169 - [c50]Oliver Schütze, Sanaz Mostaghim, Michael Dellnitz, Jürgen Teich:
Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques. EMO 2003: 118-132 - [c49]Christian Haubelt, Sanaz Mostaghim, Jürgen Teich, Ambrish Tyagi:
Solving Hierarchical Optimization Problems Using MOEAs. EMO 2003: 162-176 - [c48]Rainer Feldmann, Christian Haubelt, Burkhard Monien, Jürgen Teich:
Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. FPL 2003: 478-487 - [c47]Ali Ahmadinia, Christophe Bobda, Jürgen Teich:
Temporal task clustering for online placement on reconfigurable hardware. FPT 2003: 359-362 - [c46]Christophe Bobda, Klaus Danne, Ali Ahmadinia, Jürgen Teich:
A new approach for reconfigurable massively parallel computers. FPT 2003: 391-394 - [c45]Cornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich:
A High Performance VLIW Processor for Finite Field Arithmetic. IPDPS 2003: 189 - [c44]Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi:
FPGA designs of parallel high performance GF(2233) multipliers. ISCAS (2) 2003: 268-271 - [c43]Christian Haubelt, Dirk Koch, Jürgen Teich:
ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. SBCCI 2003: 343-348 - [c42]Sanaz Mostaghim, Jürgen Teich:
Strategies for finding good local guides in multi-objective particle swarm optimization (MOPSO). SIS 2003: 26-33 - [c41]Ali Ahmadinia, Jürgen Teich:
Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. VLSI-SOC 2003: 118-122 - [i1]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich:
Higher-Dimensional Packing with Order Constraints. CoRR cs.DS/0308006 (2003) - 2002
- [j12]Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich:
SPI - a system model for heterogeneously specified embedded systems. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 379-389 (2002) - [c40]Dirk Fischer, Jürgen Teich, Michael Thies, Ralph Weper:
Efficient architecture/compiler co-exploration for ASIPs. CASES 2002: 27-34 - [c39]Sanaz Mostaghim, Jürgen Teich, Ambrish Tyagi:
Comparison of data structures for storing Pareto-sets in MOEAs. IEEE Congress on Evolutionary Computation 2002: 843-848 - [c38]Jürgen Teich, Markus Köster:
(Self-)reconfigurable Finite State Machines: Theory and Implementation. DATE 2002: 559-566 - [c37]Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst:
System Design for Flexibility. DATE 2002: 854-861 - [c36]Marcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich:
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. IPDPS 2002 - [c35]Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi:
Tradeoff analysis of FPGA based elliptic curve cryptography. ISCAS (5) 2002: 797-800 - [c34]Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst:
Modellierung rekonfigurierbarer Systemarchitekturen. MBMV 2002: 163-171 - [c33]Marek Jersak, Kai Richter, Dirk Ziegenbein, Rolf Ernst, Christian Haubelt, Frank Slomka, Jürgen Teich:
SPI - Workbench für die Analyse Eingebetteter Systeme. Modelle, Werkzeuge und Infrastrukturen zur Unterstützung von Entwicklungsprozessen 2002: 367-368 - [c32]Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst:
Flexibility/Cost-Tradeoffs of Platform-Based Systems. Embedded Processor Design Challenges 2002: 38-56 - [c31]Jürgen Teich, Lothar Thiele:
Exact Partitioning of Affine Dependence Algorithms. Embedded Processor Design Challenges 2002: 135-153 - [c30]Marcus Bednara, Frank Hannig, Jürgen Teich:
Generation of Distributed Loop Control. Embedded Processor Design Challenges 2002: 154-170 - [c29]Frank Hannig, Jürgen Teich:
Energy estimation of nested loop programs. SPAA 2002: 149-150 - [e1]Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis:
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Lecture Notes in Computer Science 2268, Springer 2002, ISBN 3-540-43322-8 [contents] - 2001
- [j11]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich:
Extending Partial Suborders. Electron. Notes Discret. Math. 8: 34-37 (2001) - [j10]Jürgen Teich, Sándor P. Fekete, Jörg Schepers:
Optimization of Dynamic Hardware Reconfigurations. J. Supercomput. 19(1): 57-75 (2001) - [j9]Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
FunState-an internal design representation for codesign. IEEE Trans. Very Large Scale Integr. Syst. 9(4): 524-544 (2001) - [c28]Dirk Fischer, Jürgen Teich, Ralph Weper, Uwe Kastens, Michael Thies:
Design space characterization for architecture/compiler co-exploration. CASES 2001: 108-115 - [c27]Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler:
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. CODES 2001: 243-248 - [c26]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich:
Optimal FPGA module placement with temporal precedence constraints. DATE 2001: 658-667 - [c25]Jürgen Teich:
Pareto-Front Exploration with Uncertain Objectives. EMO 2001: 314-328 - [c24]Frank Hannig, Jürgen Teich:
Design Space Exploration for Massively Parallel Processor Arrays. PaCT 2001: 51-65 - [c23]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich:
Higher-Dimensional Packing with Order Constraints. WADS 2001: 300-312 - 2000
- [j8]Lothar Thiele, Jürgen Teich, Karsten Strehl:
Regular state machines. Parallel Algorithms Appl. 15(3-4): 265-300 (2000) - [j7]Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya:
Evolutionary algorithms for the synthesis of embedded software. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 452-455 (2000) - [j6]Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya:
Multidimensional Exploration of Software Implementations for DSP Algorithms. J. VLSI Signal Process. 24(1): 83-98 (2000) - [c22]Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka:
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. ASAP 2000: 299-308 - [c21]Jürgen Teich, Philipp W. Kutter, Ralph Weper:
Description and Simulation of Microprocessor Instruction Sets Using ASMs. Abstract State Machines 2000: 266-286 - [c20]Jürgen Teich, Ralph Weper, Dirk Fischer, Stefan Trinkert:
A joined architecture/compiler design environment for ASIPs. CASES 2000: 26-33 - [c19]Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya:
Optimizing the efficiency of parameterized local search within global search: a preliminary study. CEC 2000: 365-372 - [c18]F. Cieslok, H. Esau, Jürgen Teich:
EXPLORA - Generic Design Space Exploration during Embedded System Synthesis. DIPES 2000: 215-226
1990 – 1999
- 1999
- [c17]Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya:
3D exploration of software schedules for DSP algorithms. CODES 1999: 168-172 - [c16]Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
Scheduling hardware/software systems using symbolic techniques. CODES 1999: 173-177 - [c15]Kai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich:
Representation of Function Variants for Embedded System Optimization and Synthesis. DAC 1999: 517-522 - [c14]Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
FunState - an internal design representation for codesign. ICCAD 1999: 558-565 - [c13]Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich:
SPI -- An Internal Representation for Heterogeneously Specified Embedded Systems. MBMV 1999: 160-169 - [c12]Jürgen Teich, Sándor P. Fekete, Jörg Schepers:
Compile-time Optimization of Dynamic Hardware Reconfigurations. PDPTA 1999: 1097-1103 - 1998
- [j5]Tobias Blickle, Jürgen Teich, Lothar Thiele:
System-Level Synthesis Using Evolutionary Algorithms. Des. Autom. Embed. Syst. 3(1): 23-58 (1998) - [c11]Dirk Ziegenbein, Rolf Ernst, Kai Richter, Jürgen Teich, Lothar Thiele:
Combining multiple models of computation for scheduling and allocation. CODES 1998: 9-13 - [c10]Michael Eisenring, Jürgen Teich:
Domain-specific interface generation from dataflow specifications. CODES 1998: 43-47 - [c9]Michael Eisenring, Jürgen Teich:
Interfacing Hardware and Software. FPL 1998: 520-524 - [c8]Michael Eisenring, Jürgen Teich, Lothar Thiele:
Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures. HICSS (7) 1998: 187-196 - [c7]Dirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele:
Representation of process mode correlation for scheduling. ICCAD 1998: 54-61 - [c6]Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya:
Buffer Memory Optimization in DSP Applications - An Evolutionary Approach. PPSN 1998: 885-896 - 1997
- [b2]Jürgen Teich:
Digitale Hardware/Software-Systeme - Synthese und Optimierung. Springer 1997, ISBN 978-3-540-62433-2, pp. I-XVII, 1-514 - [j4]Jürgen Teich, Lothar Thiele, Sundararajan Sriram, Michael Martin:
Performance analysis and optimization of mixed asynchronous synchronous systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 473-484 (1997) - [j3]Jürgen Teich, Lothar Thiele, Lee Z. Zhang:
Partitioning Processor Arrays under Resource Constraints. J. VLSI Signal Process. 17(1): 5-20 (1997) - [c5]Jürgen Teich, Tobias Blickle, Lothar Thiele:
An evolutionary approach to system-level synthesis. CODES 1997: 167-171 - 1996
- [c4]Jürgen Teich, Lothar Thiele, Li Zhang:
Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. ASAP 1996: 131-144 - 1995
- [c3]Christian Schwarz, Jürgen Teich, Alek Vainshtein, Emo Welzl, Brian L. Evans:
Minimal Enclosing Parallelogram with Application. SCG 1995: C34-C35 - [c2]Jürgen Teich, Lothar Thiele, Edward A. Lee:
Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. ISSS 1995: 156-161 - 1993
- [b1]Jürgen Teich:
A compiler for application specific processor arrays. Saarland University, Germany, Shaker 1993, ISBN 978-3-86111-701-8, pp. 1-230 - [j2]Jürgen Teich, Lothar Thiele:
Partitioning of processor arrays: a piecewise regular approach. Integr. 14(3): 297-332 (1993) - 1992
- [c1]Jürgen Teich, Lothar Thiele:
A transformative approach to the partitioning of processor arrays. ASAP 1992: 4-20 - 1991
- [j1]Jürgen Teich, Lothar Thiele:
Control generation in the design of processor arrays. J. VLSI Signal Process. 3(1-2): 77-92 (1991)
Coauthor Index
[j126] [c487] [c479] [i40] [c464] [j104] [j103] [c459] [c449] [c448] [c440] [c430] [c422] [j94] [c414] [c408] [i26] [i24] [c393] [c391] [c387] [c378] [c369] [c368] [p15] [c357] [j60] [c336] [c328] [c307] [c305] [j51] [c275] [c272] [p9] [c247] [c228] [j39] [c205] [c190] [p6] [j33] [c151] [c134] [j27] [c122] [c106] [c103]
[c440] [j98] [j97] [j95] [c413] [c407] [c406] [b6] [j86] [j84] [c402] [c395] [c389] [j80] [j77] [j74] [c384] [c383] [c382] [c375] [c370] [p16] [p14] [i22] [j71] [j69] [c366] [c364] [c363] [c357] [c355] [c354] [c353] [c348] [j64] [j60] [c340] [c338] [c337] [c336] [c331] [c328] [j58] [j55] [c323] [c320] [c319] [c317] [c316] [c315] [c312] [c311] [c309] [c308] [c305] [c304] [c295] [c291] [p11] [p10] [c284] [c279] [c277] [c274] [c271] [c260] [c259] [c257] [c248] [c246] [c244] [c242] [j41] [c232] [c226] [c224] [c221] [c208] [c207] [c204] [c196] [c183] [c182] [c181] [c179] [c178] [c162] [c159] [c157] [c156] [c155] [c154] [c132] [c129] [c128] [j23] [c126] [c125] [c124] [c114]
[j125] [c499] [c498] [c496] [c493] [c489] [c485] [i45] [i44] [c481] [i41] [j117] [j113] [c472] [c470] [c466] [c463] [j110] [j109] [j107] [j106] [c457] [c455] [c453] [c450] [c441] [i33] [j102] [j101] [c437] [c435] [c431] [c426] [c425] [c424] [c423] [p17] [i31] [i29] [i28] [b8] [j99] [j96] [c421] [c419] [c418] [c412] [c409] [d2] [d1] [b7] [j88] [j87] [j85] [j83] [c405] [c404] [c400] [c390] [c388] [j82] [j76] [j73] [c386] [c385] [c381] [c379] [c377] [c376] [c374] [c373] [c372] [c371] [j66] [c365] [c360] [c358] [c353] [c350] [p13] [p12] [e9] [j62] [j61] [c345] [c342] [c341] [c339] [c335] [c333] [c330] [c327] [i20] [j59] [j57] [j54] [j53] [c326] [c324] [c322] [c318] [c313] [c310] [c306] [c303] [c299] [c298] [c296] [c292] [i19] [i18] [i17] [i16] [c288] [c287] [c286] [c282] [c281] [c270] [c269] [c268] [c267] [j45] [c264] [c262] [c261] [c258] [c255] [c253] [c250] [c249] [c241] [c240] [j43] [j42] [c239] [c237] [c219] [c218] [c217] [c215] [c212] [c211] [c198] [e6] [j36] [j35] [c187] [c186] [c185] [c184] [c180] [c169] [c168] [c166] [c163] [c153] [c152] [c149] [c143] [c142] [c136] [c133] [j24] [c127] [c123] [c116] [c113] [j20] [c112] [c109] [c108] [c100] [c97] [c95] [c94] [c93] [c90] [c84] [c83] [c76] [c74] [i4] [c71] [c64] [c61] [c60] [c57] [c30] [c29] [c24]
[p16] [p15] [c336] [c328] [c307] [j51] [c275] [c272] [p9] [j46] [c265] [c256] [c247] [c243] [c232] [c228] [c227] [c214] [c213] [b4] [j39] [c208] [c207] [c205] [c196] [c191] [c190] [c188] [p6] [p3] [j34] [j33] [c180] [c179] [c178] [c174] [c167] [c162] [c161] [c160] [c159] [c157] [c156] [c155] [c154] [c151] [c150] [c148] [c147] [c137] [c135] [c134] [c129] [c128] [p2] [b3] [j27] [j23] [c126] [c125] [c124] [c122] [c121] [c120] [c118] [c117] [c115] [c114] [e3] [j21] [c110] [c106] [c103] [c98] [c96] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [c85] [c79] [c78] [c59] [c55] [c51] [c49] [c48] [c43] [c37] [c34] [c33] [c32]
Jan Heisswolf
aka: Jan Heißwolf
aka: Jan Heißwolf
M. Akif Özkan
aka: M. Akif Ozkan
aka: M. Akif Ozkan
Zoran A. Salcic
aka: Zoran Salcic
aka: Zoran Salcic
Éricles Sousa
aka: Éricles Rodrigues Sousa
aka: Éricles Rodrigues Sousa
Alexandru Tanase
aka: Alexandru-Petru Tanase
aka: Alexandru-Petru Tanase
Jens Trautmann 0001
aka: Jens Schlumberger
aka: Jens Schlumberger
[j124] [j123] [c497] [c495] [c494] [c492] [c491] [c488] [c486] [j120] [j119] [c484] [c483] [c482] [c480] [c478] [c476] [j118] [j116] [j114] [j112] [j111] [c474] [c473] [c471] [c469] [c467] [c465] [c462] [i36] [i34] [j108] [c461] [c460] [c458] [c454] [c452] [c447] [c445] [c444] [i32] [c438] [c436] [c434] [c432] [c429] [c428] [i30] [j98] [j94] [c420] [c415] [c413] [c411] [c410] [i27] [b6] [j93] [j89] [j86] [j84] [c402] [c401] [c399] [c398] [c397] [c396] [c395] [c393] [j78] [c378] [c370] [c369] [c368] [c367] [i22] [j69] [c361] [c359] [c355] [c353] [c352] [c351] [c348] [c335] [c332] [c317] [c308] [c293] [j52] [c280] [j49] [j48] [c233] [c225] [c223] [c216] [p8] [c209] [c199] [c192] [c189] [c177] [c172] [c165] [c139] [c131] [c130]
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