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2020 – today
- 2024
[j9]Pudi Dhilleswararao
, Shivam Malviya, Srinivas Boppu, Yu Yang, Ahmed Hemani, Linga Reddy Cenkeramaddi:
Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework. IEEE Access 12: 124081-124094 (2024)- [j8]Yalagala Sivanjaneyulu, M. Sabarimalai Manikandan, Srinivas Boppu, Linga Reddy Cenkeramaddi:
Resource-Efficient Derivative PPG-Based Signal Quality Assessment Using One-Dimensional CNN With Optimal Hyperparameters for Quality-Aware PPG Analysis. IEEE Access 12: 141251-141267 (2024) - [j7]Pudi Dhilleswararao, Yu Yang, Dimitrios Stathis, Sunil Kumar Prajapati, Srinivas Boppu, Ahmed Hemani, Linga Reddy Cenkeramaddi:
Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study. IEEE Access 12: 155885-155903 (2024) - [j6]Pudi Dhilleswararao, Utsav Tiwari, Srinivas Boppu, Yu Yang, Ahmed Hemani:
Automating functional unit and register binding for synchoros CGRA platform. Des. Autom. Embed. Syst. 28(2): 155-186 (2024) - 2023
- [j5]Ashish Reddy Bommana, Susheel Ujwal Siddamshetty, Pudi Dhilleswararao, Arvind Thumatti K. R., Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi:
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. ACM Trans. Design Autom. Electr. Syst. 28(3): 32:1-32:35 (2023) - [c18]Pudi Dhilleswararao, Rajeev Ryansh, Vamsi Goudu, Srinivas Boppu, Ahmed Hemani:
Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures. DSD 2023: 16-23 - [c17]Yalagala Sivanjaneyulu, Srinivas Boppu, M. Sabarimalai Manikandan:
Compressive Sensing-Based Automatic PPG Signal Quality Assessment Using CNN for Energy-Constrained Medical Devices. ECAI 2023: 1-6 - [c16]Pudi Dhilleswararao, Rajeev Ryansh, Srinivas Boppu, Yu Yang, Ahmed Hemani:
Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. HEART 2023: 86-92 - [c15]Pudi Dhilleswararao, Vamsi Goudu, Srinivas Boppu, Ritika Ratnu, Ahmed Hemani:
Implementation of Image Averaging on DRRA and DiMArch Architectures. SBCCI 2023: 1-6 - [c14]Reeshita Kallapu, Dimitrios Stathis, Srinivas Boppu, Ahmed Hemani:
DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. VLSID 2023: 25-30 - 2022
- [j4]Pudi Dhilleswararao, Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi:
Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey. IEEE Access 10: 131788-131828 (2022) - [c13]Chakkapalli Manikanta Suryateja, Srinivas Boppu, Linga Reddy Cenkeramaddi, Barathram Ramkumar:
Hand Gesture Recognition System in the Complex Background for Edge Computing Devices. iSES 2022: 13-18 - [c12]Susheel Ujwal Siddamshetty, Suresh Nambi, Srinivas Boppu, Debapratim Ghosh:
Efficient Multiplication and Accumulation of Signed Numbers. iSES 2022: 130-135 - [c11]Ashish Reddy Bommana, Srinivas Boppu:
A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization. MCSoC 2022: 305-312 - [c10]Susheel Ujwal Siddamshetty, Srinivas Boppu, Debapratim Ghosh:
Efficient Hardware Architecture for Posit Addition/Subtraction. MCSoC 2022: 387-394 - 2021
- [c9]Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani:
Design and Implementation of Optimized Register File for Streaming Applications. VDAT 2021: 1-4 - 2020
- [c8]Kinjarapu Manojkumar, Srinivas Boppu, M. Sabarimalai Manikandan:
An Automated Algorithm for Estimating Respiration Rate from PPG Signals. MIND (2) 2020: 44-57 - [c7]Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich:
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT 2020: 1-6
2010 – 2019
- 2019
- [c6]Spandan Dey, Srinivas Boppu, M. Sabarimalai Manikandan:
Design of a Real-Time Automatic Source Monitoring Framework Based on Sound Source Localization. ICDIPC 2019: 35-40 - 2015
- [b1]Srinivas Boppu:
Code Generation for Tightly Coupled Processor Arrays. University of Erlangen-Nuremberg, 2015 - 2014
- [j3]Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche:
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. 13(4s): 133:1-133:29 (2014) - [j2]Srinivas Boppu, Frank Hannig, Jürgen Teich:
Compact Code Generation for Tightly-Coupled Processor Arrays. J. Signal Process. Syst. 77(1-2): 5-29 (2014) - 2013
- [c5]Srinivas Boppu, Frank Hannig, Jürgen Teich:
Loop program mapping and compact code generation for programmable hardware accelerators. ASAP 2013: 10-17 - [c4]Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich:
System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers 2013: 2:1-2:4 - 2012
- [j1]Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich:
Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. 18(1): 2:1-2:25 (2012) - [c3]Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich:
Design of Low Power On-chip Processor Arrays. ASAP 2012: 165-168 - [c2]Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich:
A prototype of an invasive tightly-coupled processor array. DASIP 2012: 1-2 - 2011
- [c1]Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade:
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig 2011: 392-397
Coauthor Index
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last updated on 2024-11-08 21:30 CET by the dblp team
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