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ORCID13th HEART 2023: Kusatsu, Japan
- Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2023, Kusatsu, Japan, June 14-16, 2023. ACM 2023
- Omar Tahir
, Wayne Luk, Nicolas Wu:
Extensible Embedded Hardware Description Languages with Compilation, Simulation and Verification. 1-10 - Mohamed A. Elgammal, Vaughn Betz:
Breaking Boundaries: Optimizing FPGA CAD with Flexible and Multi-threaded Re-Clustering. 11-18 - Karl F. A. Friebel, Jiahong Bi, Jerónimo Castrillón:
base2: An IR for Binary Numeral Types. 19-26 - Jan-Oliver Opdenhövel, Christian Plessl, Tobias Kenter:
Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation. 27-34 - Yoon Jongkwan, Yoshiki Yamaguchi, Yowichi Fujita, Yoshinori Fukao, Eitaro Hamada, Tetsuichi Kishishita, Youichi Igarashi, Masayoshi Shoji, Kazuki Ueno:
FPGA-based detector with SiC sensing for real-time monitoring of muon beams: A preliminary report of the SCIBER-1 system in COMET Phase-α. 35-40 - Hideharu Amano:
Efficient FPGA Implementation of Amoeba-inspired SAT Solver with Feedback and Bounceback Control: Harnessing Variable-Level Parallelism for Large-Scale Problem Solving in Edge Computing. 41-48 - Riadh Ben Abdelhamid, Gen Kuwazawa, Yoshiki Yamaguchi:
Quantitative study of floating-point precision on modern FPGAs. 49-58 - Jason Anderson, Boma A. Adhi, Carlos Cortes, Emanuele Del Sozzo, Omar Ragheb, Kentaro Sano:
Exploration of Compute vs. Interconnect Tradeoffs in CGRAs for HPC. 59-68 - Stewart Denholm, Wayne Luk:
Customisable Processing of Neural Networks for FPGAs. 69-77 - Md. Ashraful Islam, Kenji Kise:
Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators. 78-85 - Pudi Dhilleswararao, Rajeev Ryansh, Srinivas Boppu, Yu Yang, Ahmed Hemani:
Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. 86-92 - Muhammad Akmal Shafique, Kashif Inayat, Jeong-A Lee:
CSA Based Radix-4 Gemmini Systolic Array for Machine Learning Applications. 93-99 - Gerbrand De Laender, Erik H. D'Hollander:
ZyPy: Intercepting NumPy operations for acceleration on FPGAs. 100-106 - Mohamed A. Elgammal, Omar Mohamed Awad, Isak Edo Vivancos, Andreas Moshovos, Vaughn Betz:
cuSCNN : an Efficient CUDA Implementation of Sparse CNNs. 107-113 - Sai Sanjeet, Sannidhi Boppana, Bibhu Datta Sahoo, Masahiro Fujita:
Noise Resilience of Reduced Precision Neural Networks. 114-118
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