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ORCIDReConFig 2011: Cancun, Quintana Roo, Mexico
- Peter M. Athanas, Jürgen Becker, René Cumplido:
2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1734-5
General Sessions
- Jacob Couch
, Peter Athanas:
An Analysis of Implanted Antennas in Xilinx FPGAs. 1-6 - Diana Göhringer, Lukas Meder, Michael Hübner, Jürgen Becker:
Adaptive Multi-client Network-on-Chip Memory. 7-12 - Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers. 13-19 - Ameer Abdelhadi, Guy G. F. Lemieux:
Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations. 20-26 - Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Chuan Hong, Imanol Martinez:
Empty Resource Compaction Algorithms for Real-Time Hardware Tasks Placement on Partially Reconfigurable FPGAs Subject to Fault Ocurrence. 27-34 - Antony W. Savich, Medhat Moussa:
Resource Efficient Arithmetic Effects on RBM Neural Network Solution Quality Using MNIST. 35-40 - Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton:
Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. 41-48 - Michael Schaeferling, Gundolf Kiefer:
Object Recognition on a Chip: A Complete SURF-Based System on a Single FPGA. 49-54 - Markus Happe, Andreas Agne, Christian Plessl:
Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. 55-60 - Naveed Imran, Ronald F. DeMara:
Heterogeneous Concurrent Error Detection (hCED) Based on Output Anticipation. 61-66 - Mark G. Arnold:
Configuring Field-Programmable Robot Arrays. 67-73 - Adriano K. Sanches, João M. P. Cardoso, Alexandre C. B. Delbem:
Identifying Merge-Beneficial Software Kernels for Hardware Implementation. 74-79 - Neal Oliver, Rahul R. Sharma, Stephen Chang, Bhushan Chitlur, Elkin Garcia, Joseph Grecco, Aaron Grier, Nelson Ijih, Yaping Liu, Pratik Marolia, Henry Mitchel, Suchit Subhaschandra, Arthur Sheiman, Tim Whisonant, Prabhat Gupta:
A Reconfigurable Computing System Based on a Cache-Coherent Fabric. 80-85 - Yun Qu, Yi-Hua E. Yang, Viktor K. Prasanna:
Multi-stream Regular Expression Matching on FPGA. 86-91 - Moinuddin Sayed, Phillip H. Jones:
Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based Thermometers. 92-98 - Rizwan A. Ashraf, Ouns Mouri, Rami Jadaa, Ronald F. DeMara:
Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAs. 99-104 - Olivier Serres, Vikram K. Narayana, Tarek A. El-Ghazawi:
An Architecture for Reconfigurable Multi-core Explorations. 105-110 - Hui Zhu, Sébastien Le Beux, Nataliya Yakymets, Ian O'Connor:
Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-based Architectures. 111-116 - Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis:
Hardware OS Communication Service and Dynamic Memory Management for RSoCs. 117-122 - Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker:
Dynamic Processor Reconfiguration. 123-128 - Carl Ahlberg, Jörgen Lidholm, Fredrik Ekstrand, Giacomo Spampinato, Mikael Ekström, Lars Asplund:
GIMME - A General Image Multiview Manipulation Engine. 129-134 - Thomas Schweizer, Philipp Schlicker, Sven Eisenhardt, Tommy Kuhn, Wolfgang Rosenstiel:
Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures. 135-140 - Drausio Linardi Rossi, Vanderlei Bonato, Eduardo Marques, João Miguel Gago Pontes de Brito Lima:
A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable Computing. 141-145 - Alberto Nannarelli:
FPGA Based Acceleration of Decimal Operations. 146-151 - Cesar Ortega-Sanchez:
MiniMIPS: An 8-Bit MIPS in an FPGA for Educational Purposes. 152-157 - Thilo Pionteck, Christoph Osterloh, Carsten Albrecht:
Linking Formal Description and Simulation of Runtime Reconfigurable Systems. 158-163 - Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo:
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. 164-169
Track on High Performance Reconfigurable Computing
- Lu Sun, Hoang Le, Viktor K. Prasanna:
Optimizing Decomposition-Based Packet Classification Implementation on FPGAs. 170-175 - Tobias Becker, Qiwei Jin, Wayne Luk, Stephen Weston:
Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing. 176-181 - Xabier Iturbe, Khaled Benkrid, Ali Ebrahim, Chuan Hong, Tughrul Arslan, Imanol Martinez:
Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance Reconfigurable Computing. 182-189 - Pei Liu, Fatemeh O. Ebrahim, Ahmed Hemani, Kolin Paul:
A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics. 190-197
Track on Reconfigurable Computing for Security and Cryptography
- Suvarna Mane, Lyndon Judge, Patrick Schaumont:
An Integrated Prime-Field ECDLP Hardware Accelerator with High-Performance Modular Arithmetic Units. 198-203 - Michal Varchola, Tim Güneysu, Oliver Mischke:
MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor. 204-210 - Thomas Feller, Sunil Malipatlolla, Michael Kasper, Sorin A. Huss:
dcTPM: A Generic Architecture for Dynamic Context Management. 211-216 - Wei He, Eduardo de la Torre, Teresa Riesgo:
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. 217-222 - Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh:
Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. 223-228 - Cuautëmoc Chävez Corona, Edgar Ferrer Moreno, Francisco Rodríguez-Henríquez:
Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear Pairings. 229-234 - Bernhard Jungk, Jürgen Apfelbeck:
Area-Efficient FPGA Implementations of the SHA-3 Finalists. 235-241 - Ahmad Salman, Marcin Rogawski, Jens-Peter Kaps:
Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs. 242-248 - Benno Lomb, Tim Güneysu:
Decrypting HDCP-protected Video Streams Using Reconfigurable Hardware. 249-254 - Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez:
Robustness Analysis of Different AES Implementations on SRAM Based FPGAs. 255-260 - Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger:
Efficient Dual-Rail Implementations in FPGA Using Block RAMs. 261-267 - David M. Webster, Marcin Lukowiak:
Versatile FPGA Architecture for Skein Hashing Algorithm. 268-273 - Mieczyslaw Jessa, Lukasz Matuszewski:
Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling Method. 274-279 - Elif Bilge Kavun, Tolga Yalçin:
RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT. 280-285
Track on Reconfigurable Computing for DSP and Communications
- Marcus R. Perrett, Izzat Darwazeh:
A Simple Ethernet Stack Implementation in VHDL to Enable FPGA Logic Reconfigurability. 286-290 - Jose Hugo Barron-Zambrano, César Torres-Huitzil, Jose Juan Garcia-Hernandez:
FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual Information. 291-296 - Zhilei Chai, Jianbo Shi:
Improving KLT in Embedded Systems by Processing Oversampling Video Sequence in Real-Time. 297-302 - Eduardo Romero-Aguirre, Ramón Parra-Michel, Roberto Carrasco-Alvarez, Aldo G. Orozco-Lugo:
Architecture Based on Array Processors for Data-Dependent Superimposed Training Channel Estimation. 303-308 - Zoltan Endre Rakosi, Zheng Wang, Anupam Chattopadhyay:
Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation. 309-314 - L. R. Vela-Garcia, J. Vazquez Castillo, Ramón Parra-Michel, Alejandro Castillo Atoche:
High-Speed Stochastic Processes Generator Based on Sum-of-Sinusoids for Channel Emulation. 315-320 - Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García:
Analysis of Parallel Sorting Algorithms in K-best Sphere-Decoder Architectures for MIMO Systems. 321-326 - Dongdong Chen, Mihai Sima:
Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGA. 327-332 - Lennin C. Yllescas-Calderon, Adrian J. Espino-Orozco, Ramón Parra-Michel, Luis Fernando González Pérez:
Design and Implementation of a Simplified Turbo Decoder for 3GPP2. 333-338 - R. Zarate-Martïnez, Fernando Peña-Campos, J. Vazquez Castillo, Ramón Parra-Michel:
Arbitrary Distribution Random Variable Generator for Channel Emulators. 339-344 - Luis Manuel Ledesma-Carrillo, Eduardo Cabal-Yepez, René de Jesús Romero-Troncoso, Arturo Garcia-Perez, Roque Alfredo Osornio-Rios, Tobia D. Carozzi:
Reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n Matrices. 345-350
Track on Multiprocessor Systems and Networks on Chip
- John Aylward, Catherine H. Crawford, Ken Inoue, Scott Lekuch, Kay Müller, Mark Nutter, Hartmut Penner, Kai Schleupen, Jimi Xenidis:
Reconfigurable Systems and Flexible Programming for Hardware Design, Verification and Software Enablement for System-on-a-Chip Architectures. 351-356 - Rémi Busseuil, Lyonel Barthe, Gabriel Marchesan Almeida, Luciano Ost, Florent Bruguier, Gilles Sassatelli, Pascal Benoit, Michel Robert, Lionel Torres:
Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration. 357-362 - Hamed Sajjadi Kia, Cristinel Ababei:
Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration. 363-368 - Ye Lu, John V. McCanny, Sakir Sezer:
The Impact of Global Routing on the Performance of NoCs in FPGAs. 369-374 - J. C. Peña-Ramos, Ramón Parra-Michel:
Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core. 375-379
Track on Reconfiguration Techniques
- Patrick S. Ostler, Michael J. Wirthlin, Joshua E. Jensen:
FPGA Bootstrapping on PCIe Using Partial Reconfiguration. 380-385 - João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira:
From Instruction Traces to Specialized Reconfigurable Arrays. 386-391 - Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade:
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. 392-397 - Naveed Imran, Ronald F. DeMara:
A Self-Configuring TMR Scheme Utilizing Discrepancy Resolution. 398-403 - Kazuei Hironaka, Hideharu Amano:
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth. 404-409 - Teresa Cervero, Sebastián López, Roberto Sarmiento, Tannous Frangieh, Peter Athanas:
Scalable Models for Autonomous Self-Assembled Reconfigurable Systems. 410-415 - Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada:
Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. 416-421
Track on Productivity Environments and High Level Languages
- Andrew G. Schmidt, Ron Sass:
Improving FPGA Design and Evaluation Productivity with a Hardware Performance Monitoring Infrastructure. 422-427 - Dimitris Bekiaris, George Economakos, Efstathios Sotiriou-Xanthopoulos, Dimitrios Soudris:
Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow. 428-433 - Benjamin Thielmann, Thorsten Wink, Jens Huthmann, Andreas Koch:
RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers. 434-441 - Alexander Pacholik, Johannes Klöckner, Marcus Müller, Irina Gushchina, Wolfgang Fengler:
LiSARD: LabVIEW Integrated Softcore Architecture for Reconfigurable Devices. 442-447 - Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro:
EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. 448-454 - German Leon, Germán Fabregat, José M. Claver:
Automatic Type Inference for Resynthesis on Hardware Description Languages. 455-461
Controversy Track: FPGAs vs. GPUs
- Rafael A. Arce-Nazario, José R. Ortiz-Ubarri:
Enumeration of Costas Arrays Using GPUs and FPGAs. 462-467 - Christian de Schryver, Ivan Shcherbakov, Frank Kienle, Norbert Wehn, Henning Marxen, Anton Kostiuk, Ralf Korn:
An Energy Efficient FPGA Accelerator for Monte Carlo Option Pricing with the Heston Model. 468-474 - Hanaa M. Hussain, Khaled Benkrid, Ahmet T. Erdogan, Huseyin Seker:
Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUs. 475-480 - Alexander Pacholik, Marcus Müller, Wolfgang Fengler, Torsten Machleidt, Karl-Heinz Franke:
GPU vs FPGA: Example Application on White Light Interferometry. 481-486 - Karl Pereira, Peter Athanas, Heshan Lin, Wu Feng:
Spectral Method Characterization on FPGA and GPU Accelerators. 487-492
PhD Forum
- Azadeh Nazemi, Cesar Ortega-Sanchez, Iain Murray:
Digital Talking Book Player for the Visually Impaired Using FPGAs. 493-496 - Luis Andrés Cardona, Jharna Agrawal, Yi Guo, Joan Oliver, Carles Ferrer:
Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing Application. 497-500 - Malèk Channoufi, Pierre Lecoy, Rabah Attia, Bruno Delacressonniere, S. Garcia:
Toward All Optical Interconnections in Chip Multiprocessor (2). 501-504 - João Bispo, João M. P. Cardoso:
Techniques for Dynamically Mapping Computations to Coprocessors. 505-508 - Guillermo Conde, Gregory W. Donohoe:
Reconfigurable Block Floating Point Processing Elements in Virtex Platforms. 509-512
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