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2010 – 2019
- 2013
[j3]Malte Baesler
, Sven-Ole Voigt:
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs. Int. J. Reconfigurable Comput. 2013: 453173:1-453173:16 (2013)- 2012
- [b1]Malte Baesler:
FPGA implementation of a decimal floating-point co-processor with accurate scalar product unit. Hamburg University of Technology, Shaker 2012, ISBN 978-3-8440-1063-3, pp. 1-176 - 2011
- [c4]Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers. ReConFig 2011: 13-19 - 2010
- [j2]Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA. Int. J. Reconfigurable Comput. 2010: 357839:1-357839:13 (2010) - [j1]Sven-Ole Voigt, Malte Baesler, Thomas Teufel:
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing. J. Syst. Archit. 56(11): 561-576 (2010) - [c3]Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier. FPL 2010: 489-495 - [c2]Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
A radix-10 digit recurrence division unit with a constant digit selection function. ICCD 2010: 241-246
2000 – 2009
- 2009
- [c1]Malte Baesler, Thomas Teufel:
FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier. ReConFig 2009: 6-11
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