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ORCIDVanderlei Bonato
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2020 – today
- 2024
[c24]Pedro Henrique Di Francia Rosso
, Lucian Petrica, Nusrat Jahan Lisa, Márcio Machado Pereira, Sandro Rigo, Hervé Yviquel, Vanderlei Bonato, Emilio Francesquini, Guido Araujo:
Integrating Multi-FPGA Acceleration to OpenMP Distributed Computing. IWOMP 2024: 49-63- 2023
- [j16]Caio C. S. Oliveira, Vanderlei Bonato:
A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency. J. Signal Process. Syst. 95(4): 559-567 (2023) - 2022
- [j15]Guilherme A. Bileki, Flavio Barboza, Luiz Henrique Claudino Silva, Vanderlei Bonato:
Order book mid-price movement inference by CatBoost classifier from convolutional feature maps. Appl. Soft Comput. 116: 108274 (2022) - 2021
- [j14]Vanderlei Bonato, Christos-Savvas Bouganis:
Class-specific early exit design methodology for convolutional neural networks. Appl. Soft Comput. 107: 107316 (2021) - [j13]Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato:
Non-iterative SDC modulo scheduling for high-level synthesis. Microprocess. Microsystems 86: 104334 (2021) - [j12]André B. Perina, Arthur Silitonga, Jürgen Becker, Vanderlei Bonato:
Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis. IEEE Trans. Computers 70(12): 2070-2082 (2021)
2010 – 2019
- 2019
- [j11]Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato:
Scaling Up Modulo Scheduling for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 912-925 (2019) - [c23]André Bannwart Perina, Jürgen Becker, Vanderlei Bonato:
ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis. ICECS 2019: 618-621 - [c22]André Bannwart Perina, Jürgen Becker, Vanderlei Bonato:
Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE. FPT 2019: 343-346 - 2018
- [j10]Leandro de Souza Rosa, Aravind Dasu, Pedro C. Diniz, Vanderlei Bonato:
A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA. J. Signal Process. Syst. 90(3): 357-369 (2018) - [c21]Leandro de Souza Rosa, Vanderlei Bonato, Christos-Savvas Bouganis:
Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative Approach. FPT 2018: 62-69 - [c20]André Bannwart Perina, Vanderlei Bonato:
Mapping Estimator for OpenCL Heterogeneous Accelerators. FPT 2018: 294-297 - 2017
- [j9]Christos-Savvas Bouganis, Marek Gorgon, Vanderlei Bonato:
Special issue on applied reconfigurable computing. Microprocess. Microsystems 52: 1 (2017) - [c19]André B. Perina, Paulo Matias, Eduardo Marques, Vanderlei Bonato, João Miguel Gago Pontes de Brito Lima:
Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGA. DSD 2017: 516-519 - 2016
- [j8]Leandro de Souza Rosa, Alexandre C. B. Delbem, Claudio Fabiano Motta Toledo, Vanderlei Bonato:
Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion. Appl. Soft Comput. 49: 447-461 (2016) - [e1]Vanderlei Bonato, Christos Bouganis, Marek Gorgon:
Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings. Lecture Notes in Computer Science 9625, Springer 2016, ISBN 978-3-319-30480-9 [contents] - 2015
- [j7]Bruno de Abreu Silva, Lucas Albers Cuminato, Alexandre C. B. Delbem, Pedro C. Diniz, Vanderlei Bonato:
Application-oriented cache memory configuration for energy efficiency in multi-cores. IET Comput. Digit. Tech. 9(1): 73-81 (2015) - [c18]Helio Fernandes da Cunha Junior, Bruno de Abreu Silva, Vanderlei Bonato:
Parameterizable Ethernet Network-on-Chip Architecture on FPGA. DSD 2015: 263-266 - [c17]Bruno A. Silva, Alexandre C. B. Delbem, Vanderlei Bonato, Pedro C. Diniz:
Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems. ReConFig 2015: 1-6 - [c16]Bruno A. Silva, Lucas Albers Cuminato, Vanderlei Bonato, Pedro C. Diniz:
Run-time Cache Configuration for the LEON-3 Embedded Processor. SBCCI 2015: 42:1-42:6 - 2014
- [j6]Marcilyanne Moreira Gois, Paulo Matias, André Bannwart Perina, Vanderlei Bonato, Alexandre C. B. Delbem:
A Parallel Hardware Architecture based on Node-Depth Encoding to Solve Network Design Problems. Int. J. Nat. Comput. Res. 4(1): 54-75 (2014) - [j5]Vanderlei Bonato, Marcio Merino Fernandes, João M. P. Cardoso, Eduardo Marques:
Practical Education Fostered by Research Projects in an Embedded Systems Course. Int. J. Reconfigurable Comput. 2014: 287205:1-287205:12 (2014) - [i1]André Bannwart Perina, Marcilyanne Moreira Gois, Paulo Matias, João M. P. Cardoso, Alexandre C. B. Delbem, Vanderlei Bonato:
Representation of Evolutionary Algorithms in FPGA Cluster for Project of Large-Scale Networks. CoRR abs/1412.5384 (2014) - 2013
- [j4]Leandro de Souza Rosa, Vanderlei Bonato:
A method to convert floating to fixed-point EKF-SLAM for embedded robotics. J. Braz. Comput. Soc. 19(2): 181-192 (2013) - [j3]Vanderlei Bonato, Bruno F. Mazzotti, Marcio Merino Fernandes, Eduardo Marques:
A Mersenne Twister Hardware Implementation for the Monte Carlo Localization Algorithm. J. Signal Process. Syst. 70(1): 75-85 (2013) - 2012
- [c15]Bruno de Abreu Silva, Vanderlei Bonato:
Power/performance optimization in FPGA-based asymmetric multi-core systems. FPL 2012: 473-474 - [c14]Sergio H. M. Durand, Vanderlei Bonato:
A tool to support Bluespec SystemVerilog coding based on UML diagrams. IECON 2012: 4670-4675 - [c13]Roberto de Medeiros, Marcilyanne Moreira Gois, Vanderlei Bonato:
Designing FPGA-based embedded systems with MARTE: A PIM to PSM converter. IECON 2012: 4682-4687 - [c12]Bruno de Abreu Silva, Lucas Albers Cuminato, Vanderlei Bonato:
Reducing the overall cache miss rate using different cache sizes for Heterogeneous Multi-core Processors. ReConFig 2012: 1-6 - [c11]Roberto de Medeiros, Miguel Góis, Drausio Linardi Rossi, Vanderlei Bonato:
Designing embedded systems with MARTE: A PIM to PSM converter. SIES 2012: 303-306 - 2011
- [c10]Drausio Linardi Rossi, Vanderlei Bonato, Eduardo Marques, João Miguel Gago Pontes de Brito Lima:
A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable Computing. ReConFig 2011: 141-145
2000 – 2009
- 2009
- [j2]Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots. J. Signal Process. Syst. 56(1): 41-50 (2009) - [c9]Vanderlei Bonato, Eduardo Marques:
RoboArch: A component-based tool proposal for developing hardware architecture for mobile robots. SIES 2009: 249-252 - 2008
- [b1]Vanderlei Bonato:
Proposal of an FPGA hardware architecture for SLAM using multi-cameras and applied to mobile robotics (Proposta de uma arquitetura de hardware em FPGA implementada para SLAM com multi-câmeras aplicada à robótica móvel). University of São Paulo, Brazil, 2008 - [j1]Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection. IEEE Trans. Circuits Syst. Video Technol. 18(12): 1703-1712 (2008) - [c8]Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A Parallel Hardware Architecture for Image Feature Detection. ARC 2008: 136-147 - 2007
- [c7]Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A floating-point Extended Kalman Filter implementation for autonomous mobile robots. FPL 2007: 576-579 - [c6]Vanderlei Bonato, Rafael Peron, Denis F. Wolf, José A. M. de Holanda, Eduardo Marques, João M. P. Cardoso:
An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics. SIES 2007: 148-155 - 2006
- [c5]Vanderlei Bonato, José A. M. de Holanda, Eduardo Marques:
An Embedded Multi-camera System for Simultaneous Localization and Mapping. ARC 2006: 109-114 - 2004
- [c4]Vanderlei Bonato, Adriano K. Sanches, Marcio Merino Fernandes, João M. P. Cardoso, Eduardo do Valle Simões, Eduardo Marques:
A Real Time Gesture Recognition System for Mobile Robots. ICINCO (2) 2004: 207-214 - [c3]Vanderlei Bonato, Ricardo Menotti, Eduardo do Valle Simões, Marcio Merino Fernandes, Eduardo Marques:
Teaching embedded systems with FPGAs throughout a computer science course. WCAE 2004: 4 - 2003
- [c2]Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes:
Design of a fingerprint system using a hardware/software environment. FPGA 2003: 240 - [c1]Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes:
Propose of a Hardware Implementation for Fingerprint Systems. FPL 2003: 1158-1161
Coauthor Index
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