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ORCIDZoltán Endre Rákossy
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- affiliation: RWTH Aachen University, Germany
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2010 – 2019
- 2015
[c16]Zoltán Endre Rákossy, Dominik Stengele, Axel Acosta-Aponte, Saumitra Chafekar, Paolo Bientinesi, Anupam Chattopadhyay:
Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. ARC 2015: 301-310- [c15]Zoltán Endre Rákossy, Axel Acosta-Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay:
Design and synthesis of reconfigurable control-flow structures for CGRA. ReConFig 2015: 1-8 - [c14]Zoltán Endre Rákossy, Dominik Stengele, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay:
Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture. VLSI-SoC 2015: 337-342 - 2014
- [c13]Zoltán Endre Rákossy, Farhad Merchant
, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay:
Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. ASAP 2014: 188-189 - [c12]Alexander Fell, Zoltán Endre Rákossy, Anupam Chattopadhyay:
Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures. ReConFig 2014: 1-8 - [c11]Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay:
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation. VLSI-SoC 2014: 1-6 - [c10]Zoltán Endre Rákossy:
Modeling, analysis and exploration of layers: A 3D computing architecture. VLSI-SoC 2014: 159-160 - 2013
- [c9]Khawar Shahzad, Ayesha Khalid, Zoltán Endre Rákossy, Goutam Paul, Anupam Chattopadhyay:
CoARX: a coprocessor for ARX-based cryptographic algorithms. DAC 2013: 133:1-133:10 - [c8]Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi:
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. DATE 2013: 535-540 - [c7]Zoltán Endre Rákossy, Axel Acosta-Aponte, Anupam Chattopadhyay:
Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC. ReConFig 2013: 1-6 - 2012
- [j2]Zoltán Endre Rákossy, Zheng Wang, Anupam Chattopadhyay:
High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures. Int. J. Reconfigurable Comput. 2012: 961950:1-961950:20 (2012) - [c6]Zoltán Endre Rákossy, Tejas Naphade, Anupam Chattopadhyay:
Design and analysis of layered coarse-grained reconfigurable architecture. ReConFig 2012: 1-6 - [c5]Zheng Wang, Xiao Wang, Anupam Chattopadhyay, Zoltan Endre Rakosi:
ASIC synthesis using Architecture Description Language. VLSI-DAT 2012: 1-4 - 2011
- [c4]Zoltan Endre Rakosi, Zheng Wang, Anupam Chattopadhyay:
Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation. ReConFig 2011: 309-314 - [c3]Anupam Chattopadhyay, Zoltan Endre Rakosi:
Combinational logic synthesis for material implication. VLSI-SoC 2011: 200-203
2000 – 2009
- 2009
- [c2]Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura:
Hot-Swapping architecture extension for mitigation of permanent functional unit faults. FPL 2009: 578-581 - 2008
- [j1]Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embed. Comput. Syst. 7(4): 40:1-40:31 (2008) - 2007
- [c1]Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. IEEE International Workshop on Rapid System Prototyping 2007: 189-194
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