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ORCIDS. K. Nandy 0001
Soumitra Kumar Nandy
Person information
- affiliation: Indian Institute of Science (IISc), Department of Computational and Data Sciences, CAD Laboratory, Bangalore, India
- affiliation: ERNET, India
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2020 – today
- 2022
[j31]Oscar Ferraz
, Srinivasan Subramaniyan, Ramesh Chinthalaa, João Andrade, Joseph R. Cavallaro, Soumitra Kumar Nandy, Vítor Silva, Xinmiao Zhang, Madhura Purnaprajna, Gabriel Falcão:
A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures. IEEE Commun. Surv. Tutorials 24(1): 524-556 (2022)- [i6]Harish Agrawal, Sumana T., S. K. Nandy:
Symmetric Convolutional Filters: A Novel Way to Constrain Parameters in CNN. CoRR abs/2202.13099 (2022) - 2021
- [j30]Pavel G. Emelyanov, Madhava Krishna C, Vadiraj Kulkarni, S. K. Nandy, Denis K. Ponomaryov, Soumyendu Raha:
Factorization of Boolean Polynomials: Parallel Algorithms and Experimental Evaluation. Program. Comput. Softw. 47(2): 108-118 (2021) - 2020
- [j29]Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy:
Towards Accelerated Genome Informatics on Parallel HPC Platforms: The ReneGENE-GI Perspective. J. Signal Process. Syst. 92(10): 1197-1213 (2020)
2010 – 2019
- 2019
- [j28]Ipsita Biswas Mahapatra, S. K. Nandy:
EX-DRIVE: An Execution Driven Functional Verification Flow. J. Low Power Electron. 15(2): 168-181 (2019) - [c120]Vadiraj Kulkarni, Pavel G. Emelyanov, Denis K. Ponomaryov, Madhava Krishna C, Soumyendu Raha, S. K. Nandy:
Parallel Factorization of Boolean Polynomials. Ershov Informatics Conference 2019: 80-94 - [c119]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSID 2019: 64-69 - [c118]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Applying Modified Householder Transform to Kalman Filter. VLSID 2019: 431-436 - 2018
- [j27]Mahnaz Mohammadi, Akhil Krishna, Nalesh Sivanandan, S. K. Nandy:
A Hardware Architecture for Radial Basis Function Neural Network Classifier. IEEE Trans. Parallel Distributed Syst. 29(3): 481-495 (2018) - [j26]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. IEEE Trans. Parallel Distributed Syst. 29(8): 1707-1720 (2018) - [c117]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. ARC 2018: 119-131 - [c116]Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy:
ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs. ARC 2018: 178-191 - [c115]Santhi Natarajan, N. Krishna Kumar, H. V. Anuchan, Debnath Pal, S. K. Nandy:
ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads. ARC 2018: 564-577 - [c114]Ipsita Biswas Mahapatra, S. K. Nandy:
An Algorithm - Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification. ISED 2018: 85-89 - [c113]Ipsita Biswas Mahapatra, Utkarsh Agarwal, Chandrashekhar Azad, S. K. Nandy:
Design Space Exploration of an Execution-Driven Functional Simulation Methodology. VLSID 2018: 295-300 - [i5]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design. CoRR abs/1802.03650 (2018) - [i4]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR abs/1803.05320 (2018) - 2017
- [j25]Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan:
Energy aware synthesis of application kernels through composition of data-paths on a CGRA. Integr. 58: 320-328 (2017) - [j24]Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. Parallel Process. Lett. 27(3-4): 1750006:1-1750006:17 (2017) - [c112]Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, François Neumann, Philippe Baufreton:
REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress). CASES 2017: 15:1-15:2 - [e1]Yale N. Patt, S. K. Nandy:
2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017, Pythagorion, Greece, July 17-20, 2017. IEEE 2017, ISBN 978-1-5386-3437-0 [contents] - 2016
- [j23]Arnab Kumar Biswas, S. K. Nandy:
Role based shared memory access control mechanisms in NoC based MP-SoC. Nano Commun. Networks 7: 46-64 (2016) - [j22]Gopinath Mahale, Hamsika Mahale, S. K. Nandy, Ranjani Narayan:
REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores. IEEE Trans. Parallel Distributed Syst. 27(12): 3602-3616 (2016) - [c111]Mahnaz Mohammadi, Rohit Ronge, Sanjay S. Singapuram, S. K. Nandy:
Performance Evaluation of Feed-Forward Backpropagation Neural Network for Classification on a Reconfigurable Hardware Architecture. ARC 2016: 312-319 - [c110]Kavitha T. Madhu, Anuj Rao, Saptarsi Das, Krishna C. Madhava, S. K. Nandy, Ranjani Narayan:
Flexible resource allocation and management for application graphs on ReNÉ MPSoC. PARMA-DITAM@HiPEAC 2016: 13-18 - [c109]Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy:
AccuRA: Accurate alignment of short reads on scalable reconfigurable accelerators. SAMOS 2016: 79-87 - [c108]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. VLSID 2016: 98-103 - [c107]Ashish Kumar Pradhan, Soumitra Kumar Nandy:
An Energy Efficient Dynamically Reconfigurable QR Decomposition for Wireless MIMO Communication. VLSID 2016: 276-281 - [c106]Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan:
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. VLSID 2016: 391-396 - [c105]Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan:
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. VLSID 2016: 391-396 - [c104]Farhad Merchant, Nimash Choudhary, S. K. Nandy, Ranjani Narayan:
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. VLSID 2016: 415-420 - [c103]Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan:
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. VLSID 2016: 601-602 - [i3]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design. CoRR abs/1610.06385 (2016) - [i2]Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. CoRR abs/1610.08705 (2016) - [i1]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR abs/1612.04470 (2016) - 2015
- [j21]Arnab Kumar Biswas, S. K. Nandy, Ranjani Narayan:
Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat. Circuits Syst. Signal Process. 34(10): 3241-3290 (2015) - [j20]S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. J. Low Power Electron. 11(3): 426-435 (2015) - [c102]Pratima Ashok Dhuldhule, J. Lakshmi, S. K. Nandy:
High Performance Computing Cloud - A Platform-as-a-Service Perspective. CCBD 2015: 21-28 - [c101]Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Compiling HPC Kernels for the REDEFINE CGRA. HPCC/CSS/ICESS 2015: 405-410 - [c100]Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan:
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. iNIS 2015: 7-12 - [c99]Vaibhav Ankush Kachore, J. Lakshmi, S. K. Nandy:
Location Obfuscation for Location Data Privacy. SERVICES 2015: 213-220 - [c98]Mahnaz Mohammadi, Rohit Ronge, Jayesh Ramesh Chandiramani, Soumitra Kumar Nandy:
An accelerator for classification using radial basis function neural network. SoCC 2015: 137-142 - [c97]Alexander Fell, S. K. Nandy, Ranjani Narayan:
A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address. SoCC 2015: 191-196 - [c96]Gopinath Mahale, Hamsika Mahale, Arnav Goel, S. K. Nandy, S. Bhattacharya, Ranjani Narayan:
Hardware Solution for Real-Time Face Recognition. VLSID 2015: 81-86 - [c95]Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna C, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. VLSID 2015: 153-158 - [c94]Mahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh R. Chandiramani, S. K. Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan, Sukumar Bhattacharya:
A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks. VLSID 2015: 505-510 - 2014
- [j19]Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan:
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. J. Syst. Archit. 60(7): 592-614 (2014) - [c93]Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay:
Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. ASAP 2014: 188-189 - [c92]Pavan Kumar Akulakrishna, J. Lakshmi, S. K. Nandy:
Efficient Storage of Big-Data for Real-Time GPS Applications. BDCloud 2014: 1-8 - [c91]Aakriti Gupta, J. Lakshmi, S. K. Nandy:
Real Time Routing in Road Networks. BDCloud 2014: 9-16 - [c90]Gopinath Mahale, Hamsika Mahale, Rajesh Babu Parimi, S. K. Nandy, S. Bhattacharya:
Hardware architecture of bi-cubic convolution interpolation for real-time image scaling. FPT 2014: 264-267 - [c89]S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. ISED 2014: 20-24 - [c88]Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. ICSAMOS 2014: 215-224 - [c87]Mahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S. K. Nandy, Ranjani Narayan:
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs. ICSAMOS 2014: 225-232 - [c86]Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay:
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation. VLSI-SoC 2014: 1-6 - [c85]Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan:
Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). VLSID 2014: 258-263 - 2013
- [c84]Mohit Dhingra, J. Lakshmi, S. K. Nandy, Chiranjib Bhattacharyya, Kanchi Gopinath:
Elastic Resources Framework in IaaS, Preserving Performance SLAs. IEEE CLOUD 2013: 430-437 - [c83]Ankit Anand, J. Lakshmi, S. K. Nandy:
Virtual Machine Placement Optimization Supporting Performance SLAs. CloudCom (1) 2013: 298-305 - [c82]S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan:
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. ISCAS 2013: 3034-3037 - [c81]Abhijit Giri, S. K. Nandy:
Optimal Pipeline Depth and Supply Voltage for Power-constrained Processors. VLSI Design 2013: 37-42 - 2012
- [c80]Mohit Dhingra, J. Lakshmi, S. K. Nandy:
Resource Usage Monitoring in Clouds. GRID 2012: 184-191 - 2011
- [j18]Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan:
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 4: 193-209 (2011) - [c79]Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC 2011: 125-132 - [c78]Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy:
Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture. FPT 2011: 1-5 - [c77]Saptarsi Das, Ranjani Narayan, Soumitra Kumar Nandy:
Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields. ICETE (Selected Papers) 2011: 249-263 - [c76]Alok Baluni, Farhad Merchant, S. K. Nandy, Srinivasan Balakrishnan:
A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support. ISED 2011: 45-50 - [c75]Adarsha Rao, S. K. Nandy, Hristo Nikolov, Ed F. Deprettere:
USHA: Unified software and hardware architecture for video decoding. SASP 2011: 30-37 - [c74]Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy:
A Method for Flexible Reduction over Binary Fields using a Field Multiplier. SECRYPT 2011: 50-58 - 2010
- [c73]J. Lakshmi, S. K. Nandy:
I/O Virtualization Architecture for Security. CIT 2010: 2267-2272 - [c72]Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita:
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES 2010: 77-86 - [c71]Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI 2010: 161-166 - [c70]N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. ICSAMOS 2010: 178-184 - [c69]Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS 2010: 265-272
2000 – 2009
- 2009
- [j17]Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan:
REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9(2): 11:1-11:48 (2009) - [c68]Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan:
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC 2009: 204-215 - [c67]Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, Sreeramula Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan:
An Input Triggered Polymorphic ASIC for H.264 Decoding. ASAP 2009: 106-113 - [c66]Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan:
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES 2009: 127-136 - [c65]J. Lakshmi, S. K. Nandy:
I/O Device Virtualization in the Multi-core era, a QoS Perspective. GPC Workshops 2009: 128-135 - [c64]Ritesh Rajore, S. K. Nandy, H. S. Jamadagni:
Architecture of Run-Time Reconfigurable Channel Decoder. ICC 2009: 1-6 - [c63]A. N. Satrawala, S. K. Nandy:
RETHROTTLE: Execution throttling in the REDEFINE SoC architecture. ICSAMOS 2009: 82-91 - [c62]Ganesh Garga, David Guevorkian, S. K. Nandy, H. S. Jamadagni:
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures. ICSAMOS 2009: 157-164 - [c61]Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan:
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. SoCC 2009: 251-254 - 2008
- [j16]Subhasis Banerjee, G. Surendra, S. K. Nandy:
On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. J. Syst. Archit. 54(8): 797-815 (2008) - [c60]Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan:
Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP 2008: 13-18 - [c59]Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy:
Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. ASAP 2008: 49-54 - [c58]Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan:
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP 2008: 251-256 - [c57]Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. ASAP 2008: 287-292 - [c56]Ganesh Garga, Mythri Alle, Keshavan Varadarajan, S. K. Nandy, H. S. Jamadagni:
Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network. SoC 2008: 1-4 - 2007
- [j15]Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy:
Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electron. 3(1): 106-118 (2007) - [c55]Subhasis Banerjee, G. Surendra, S. K. Nandy:
Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. ASP-DAC 2007: 884-889 - [c54]A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. FPL 2007: 558-561 - 2006
- [j14]G. Surendra, Subhasis Banerjee, S. K. Nandy:
Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. J. Embed. Comput. 2(1): 15-34 (2006) - [c53]Raghu Anantharangachar, Gorur N. Shrinivas, S. K. Nandy:
Towards Self-Composing, Prioritized and Consequential Services. IEEE SCC 2006: 518 - [c52]K. Kalapriya, S. K. Nandy, Nanjangud C. Narendra:
A Framework for Measurement of End-To-End Qos Requirements in Loosely Coupled Systems. AINA (2) 2006: 926 - [c51]Sandeep B. Singh, Jayanta Biswas, S. K. Nandy:
A Cost Effective Pipelined Divider for Double Precision Floating Point Number. ASAP 2006: 132-137 - [c50]Mythri Alle, Jayanta Biswas, S. K. Nandy:
High Performance VLSI Architecture Design for H.264 CAVLC Decoder. ASAP 2006: 317-322 - [c49]Jayanta Biswas, Soumitra Kumar Nandy:
Efficient Key Management and Distribution for MANET. ICC 2006: 2256-2261 - [c48]K. Kalapriya, S. K. Nandy:
On the Implementation of a Streaming Video over Peer to Peer network using Middleware Components. ICN/ICONS/MCL 2006: 59 - [c47]J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan:
Framework for Enabling Highly Available Distributed Applications for Utility Computing. ISPA 2006: 549-560 - [c46]Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell:
Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. MICRO 2006: 433-442 - 2005
- [c45]K. Kalapriya, S. K. Nandy:
Throughput Driven, Highly Available Streaming Stored Playback Video Service over a Peer-to-Peer Network. AINA 2005: 229-234 - [c44]K. C. Nainwal, J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan:
A Framework for QoS Adaptive Grid Meta Scheduling. DEXA Workshops 2005: 292-296 - [c43]Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy:
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. ITC 2005: 9 - [c42]Nanjangud C. Narendra, Umesh Bellur, S. K. Nandy, K. Kalapriya:
Functional and architectural adaptation in pervasive computing environments. MPAC 2005: 1-7 - 2004
- [j13]H. Sarojadevi, S. K. Nandy, Srinivasan Balakrishnan:
On the Correctness of Program Execution When Cache Coherence Is Maintained Locally at Data-Sharing Boundaries in Distributed Shared Memory Multiprocessors. Int. J. Parallel Program. 32(5): 415-446 (2004) - [c41]K. Kalapriya, S. K. Nandy, K. Venkatesh Babu:
Can Streaming Of Stored Playback Video Be Supported On Peer to Peer Infrastructure? AINA (2) 2004: 200-203 - [c40]G. Surendra, Subhasis Banerjee, S. K. Nandy:
Power-performance trade-off using pipeline delays. ASP-DAC 2004: 384-386 - [c39]Subhasis Banerjee, G. Surendra, S. K. Nandy:
Exploiting program execution phases to trade power and performance for media workload. ASP-DAC 2004: 387-389 - [c38]K. Kalapriya, S. K. Nandy, Deepti Srinivasan, R. Uma Maheshwari, V. Satish:
A framework for resource discovery in pervasive computing for mobile aware task execution. Conf. Computing Frontiers 2004: 70-77 - [c37]K. Kalapriya, S. K. Nandy, V. Satish, R. Uma Maheshwari, Deepti Srinivas:
An Architectural View of the Entities Required for Execution of Task in Pervasive Space. FTDCS 2004: 37-43 - [c36]K. Kalapriya, K. Venkatesh Babu, Soumitra Kumar Nandy:
Streaming stored playback video over a peer-to-peer network. ICC 2004: 1298-1302 - [c35]G. Surendra, Subhasis Banerjee, S. K. Nandy:
On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. WMPI 2004: 88-95 - 2003
- [j12]G. Surendra, Subhasis Banerjee, S. K. Nandy:
On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. Int. J. Parallel Program. 31(6): 469-487 (2003) - [c34]Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran:
Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. Asia-Pacific Computer Systems Architecture Conference 2003: 166-179 - [c33]M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy:
A complexity effective communication model for behavioral modeling of signal processing applications. DAC 2003: 412-415 - [c32]G. Surendra, Subhasis Banerjee, S. K. Nandy:
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. DATE 2003: 10784-10789 - [c31]K. Kalapriya, B. R. Raghucharan, Abhijit M. Lele, S. K. Nandy:
Traffic Profiling for Efficient Network Resource Utilization. International Conference on Internet Computing 2003: 789-795 - [c30]Amitabh Menon, S. K. Nandy, Mahesh Mehendale:
Multivoltage scheduling with voltage-partitioned variable storage. ISLPED 2003: 298-301 - [p1]G. Surendra, Subhasis Banerjee, S. K. Nandy:
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. Embedded Software for SoC 2003: 359-371 - 2002
- [c29]H. Sarojadevi, S. K. Nandy, Srinivasan Balakrishnan:
Enforcing Cache Coherence at Data Sharing Boundaries without Global Control: A Hardware-Software Approach (Research Note). Euro-Par 2002: 543-546 - [c28]Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan:
Speculative Trace Scheduling in VLIW Processors. ICCD 2002: 408-413 - [c27]Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan:
On the Benefits of Speculative Trace Scheduling in VLIW Processors. PDPTA 2002: 822-828 - [c26]Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishanan:
Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW Processors. SBCCI 2002: 43-48 - 2001
- [c25]Arshad Ahmed, S. K. Nandy, Paul Sathya:
Content adaptive motion estimation for mobile video encoders. ISCAS (2) 2001: 237-240 - [c24]G. Surendra, S. K. Nandy, Paul Sathya:
ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. VLSI Design 2001: 85-90 - [c23]Abhijit M. Lele, S. K. Nandy:
Architecture of Reconfigurable a Low Power Gigabit AT Switch. VLSI Design 2001: 242-247 - 2000
- [j11]Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema:
Harmony - An Architecture for Providing Quality of Service in Mobile Computing Environments. J. Interconnect. Networks 1(3): 247-266 (2000) - [j10]S. Ramanathan, S. K. Nandy, V. Visvanathan:
Reconfigurable Filter Coprocessor Architecture for DSP Applications. J. VLSI Signal Process. 26(3): 333-359 (2000) - [c22]M. Srikanth Rao, S. K. Nandy:
Power minimization using control generated clocks. DAC 2000: 794-799 - [c21]Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema:
Design Space Exploration for Orividing QoS Within the Harmony Framework. IEEE International Conference on Multimedia and Expo (I) 2000: 521-524 - [c20]Srikunth Rao M., Soumitra Kumar Nandy:
Controller redesign based clock and register power minimization. ISCAS 2000: 275-278 - [c19]Srinivasan Balakrishnan, Soumitra Kumar Nandy:
Performance evaluation of multithreaded architectures for media processing applications. ISCAS 2000: 531-534
1990 – 1999
- 1999
- [j9]S. Ramanathan, V. Visvanathan, S. K. Nandy:
Synthesis of ASIPs for DSP algorithms. Integr. 28(1): 13-32 (1999) - [j8]S. Ramanathan, V. Visvanathan, S. K. Nandy:
A computational engine for multirate FIR digital filtering. Signal Process. 79(2): 213-222 (1999) - [j7]S. Ramanathan, V. Visvanathan, S. K. Nandy:
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. J. VLSI Signal Process. 22(3): 173-195 (1999) - [c18]Abhijit M. Lele, S. K. Nandy:
Harmony - A Framework for Providing Quality of Service in Wireless Mobile Computing Environment. HiPC 1999: 299-308 - [c17]Avinash K. Gautam, V. Visvanathan, S. K. Nandy:
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ICCD 1999: 285-288 - [c16]S. Ramanathan, V. Visvanathan, S. K. Nandy:
Synthesis of Configurable Architectures for DSP Algorithms. VLSI Design 1999: 350-357 - 1998
- [c15]Srinivasan Balakrishnan, Soumitra Kumar Nandy:
Arbitrary Precision Arithmetic - SIMD Style. VLSI Design 1998: 128-132 - 1997
- [j6]Vinod Menezes, S. K. Nandy, Biswadip Mitra:
Signal compression through spatial frequency-based motion estimation. Integr. 22(1-2): 115-135 (1997) - [c14]M. R. Karthikeyan, Soumitra Kumar Nandy:
An asynchronous architecture for digital signal processors. ED&TC 1997: 615 - [c13]Srinivasan Balakrishnan, S. K. Nandy, Arjan J. C. van Gemund:
Modeling multi-threaded architectures in PAMELA for real-time high performance applications. HiPC 1997: 407-414 - 1996
- [c12]Vinod Menezes, Soumitra Kumar Nandy, Biswadip Mitra:
Spatial frequency based motion estimation for image sequence compression. HiPC 1996: 257-262 - 1995
- [j5]Debabrata Ghosh, S. K. Nandy:
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 36-48 (1995) - [c11]Debabrata Ghosh, Soumitra Kumar Nandy:
Wave pipelined architecture folding: a method to achieve low power and low area. VLSI Design 1995: 184- - 1994
- [j4]S. K. Nandy, R. B. Panwar:
Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors. VLSI Design 1(2): 127-154 (1994) - [j3]S. K. Nandy:
Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment. VLSI Design 1(2): 155-167 (1994) - [c10]Debabrata Ghosh, S. K. Nandy, K. Parthasarathy:
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. VLSI Design 1994: 77-82 - [c9]Debabrata Ghosh, Shamik Sural, S. K. Nandy:
A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. VLSI Design 1994: 95-100 - [c8]G. N. Rathna, S. K. Nandy, K. Parthasarathy:
A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. VLSI Design 1994: 225-228 - [c7]Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal:
High Speed Digital Filtering on SRAM-Based FPGAs. VLSI Design 1994: 229-232 - 1993
- [c6]Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy:
Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. DAC 1993: 303-307 - [c5]Debabrata Ghosh, S. K. Nandy:
A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. ICCD 1993: 198-201 - [c4]S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan:
A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. ICPP (3) 1993: 94-97 - [c3]Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan:
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. VLSI Design 1993: 341-346 - 1990
- [j2]S. Balakrishnan, S. K. Nandy:
Quasi dynamic approach to layout compaction. Microprocessing and Microprogramming 30(1-5): 231-236 (1990) - [j1]C. E. Prakash, S. K. Nandy:
VOXEL based modeling and rendering irregular solids. Microprocessing and Microprogramming 30(1-5): 341-346 (1990)
1980 – 1989
- 1989
- [c2]Narasimha B. Bhat, S. K. Nandy:
Special Purpose Architecture for Accelerating Bitmap DRC. DAC 1989: 674-677 - 1986
- [c1]S. K. Nandy, L. V. Ramakrishnan:
Dual quadtree representation for VLSI designs. DAC 1986: 663-666
Coauthor Index
[c119] [c118] [j26] [c117] [i5] [i4] [j25] [j24] [c112] [j22] [c110] [c108] [c106] [c105] [c104] [c103] [i3] [i2] [i1] [j21] [j20] [c101] [c100] [c97] [c96] [c95] [c94] [j19] [c89] [c88] [c87] [c85] [c82] [j18] [c79] [c77] [c74] [c72] [c71] [c70] [c69] [j17] [c68] [c67] [c66] [c61] [c60] [c58] [c57] [c54] [c47] [c44] [c4]
Nalesh S 0001
aka: Nalesh Sivanandan
aka: Nalesh Sivanandan
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