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2010 – 2019
- 2019
[c38]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSID 2019: 64-69- [c37]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Applying Modified Householder Transform to Kalman Filter. VLSID 2019: 431-436 - 2018
- [j10]Farhad Merchant
, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. IEEE Trans. Parallel Distributed Syst. 29(8): 1707-1720 (2018) - [c36]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. ARC 2018: 119-131 - [i5]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design. CoRR abs/1802.03650 (2018) - [i4]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR abs/1803.05320 (2018) - 2017
- [j9]Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan:
Energy aware synthesis of application kernels through composition of data-paths on a CGRA. Integr. 58: 320-328 (2017) - [j8]Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. Parallel Process. Lett. 27(3-4): 1750006:1-1750006:17 (2017) - [c35]Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, François Neumann, Philippe Baufreton:
REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress). CASES 2017: 15:1-15:2 - 2016
- [j7]Gopinath Mahale, Hamsika Mahale, S. K. Nandy, Ranjani Narayan:
REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores. IEEE Trans. Parallel Distributed Syst. 27(12): 3602-3616 (2016) - [c34]Kavitha T. Madhu, Anuj Rao, Saptarsi Das, Krishna C. Madhava, S. K. Nandy, Ranjani Narayan:
Flexible resource allocation and management for application graphs on ReNÉ MPSoC. PARMA-DITAM@HiPEAC 2016: 13-18 - [c33]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. VLSID 2016: 98-103 - [c32]Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan:
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. VLSID 2016: 391-396 - [c31]Farhad Merchant, Nimash Choudhary, S. K. Nandy, Ranjani Narayan:
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. VLSID 2016: 415-420 - [c30]Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan:
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. VLSID 2016: 601-602 - [i3]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design. CoRR abs/1610.06385 (2016) - [i2]Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. CoRR abs/1610.08705 (2016) - [i1]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR abs/1612.04470 (2016) - 2015
- [j6]Arnab Kumar Biswas, S. K. Nandy, Ranjani Narayan:
Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat. Circuits Syst. Signal Process. 34(10): 3241-3290 (2015) - [j5]S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. J. Low Power Electron. 11(3): 426-435 (2015) - [c29]Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Compiling HPC Kernels for the REDEFINE CGRA. HPCC/CSS/ICESS 2015: 405-410 - [c28]Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan:
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. iNIS 2015: 7-12 - [c27]Alexander Fell, S. K. Nandy, Ranjani Narayan:
A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address. SoCC 2015: 191-196 - [c26]Gopinath Mahale, Hamsika Mahale, Arnav Goel, S. K. Nandy, S. Bhattacharya, Ranjani Narayan:
Hardware Solution for Real-Time Face Recognition. VLSID 2015: 81-86 - [c25]Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna C, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. VLSID 2015: 153-158 - [c24]Mahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh R. Chandiramani, S. K. Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan, Sukumar Bhattacharya:
A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks. VLSID 2015: 505-510 - 2014
- [j4]Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan:
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. J. Syst. Archit. 60(7): 592-614 (2014) - [c23]S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. ISED 2014: 20-24 - [c22]Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. ICSAMOS 2014: 215-224 - [c21]Mahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S. K. Nandy, Ranjani Narayan:
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs. ICSAMOS 2014: 225-232 - [c20]Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan:
Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). VLSID 2014: 258-263 - 2013
- [c19]S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan:
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. ISCAS 2013: 3034-3037 - 2011
- [j3]Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan:
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 4: 193-209 (2011) - [c18]Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC 2011: 125-132 - [c17]Saptarsi Das, Ranjani Narayan, Soumitra Kumar Nandy:
Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields. ICETE (Selected Papers) 2011: 249-263 - [c16]Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy:
A Method for Flexible Reduction over Binary Fields using a Field Multiplier. SECRYPT 2011: 50-58 - 2010
- [c15]Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita:
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES 2010: 77-86 - [c14]Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI 2010: 161-166 - [c13]N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. ICSAMOS 2010: 178-184 - [c12]Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS 2010: 265-272
2000 – 2009
- 2009
- [j2]Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan:
REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9(2): 11:1-11:48 (2009) - [c11]Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan:
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC 2009: 204-215 - [c10]Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, Sreeramula Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan:
An Input Triggered Polymorphic ASIC for H.264 Decoding. ASAP 2009: 106-113 - [c9]Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan:
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES 2009: 127-136 - [c8]Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan:
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. SoCC 2009: 251-254 - 2008
- [c7]Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan:
Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP 2008: 13-18 - [c6]Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan:
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP 2008: 251-256 - [c5]Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. ASAP 2008: 287-292 - 2007
- [c4]A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. FPL 2007: 558-561 - 2006
- [c3]J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan:
Framework for Enabling Highly Available Distributed Applications for Utility Computing. ISPA 2006: 549-560 - 2005
- [c2]K. C. Nainwal, J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan:
A Framework for QoS Adaptive Grid Meta Scheduling. DEXA Workshops 2005: 292-296
1990 – 1999
- 1993
- [c1]S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan:
A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. ICPP (3) 1993: 94-97 - 1990
- [j1]Ranjani Narayan, V. Rajaraman:
Performance analysis of a multiprocessor machine based on data flow principles. Microprocessing and Microprogramming 30(1-5): 601-608 (1990)
Coauthor Index
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