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ORCIDCASES 2017: Seoul, Republic of Korea
- Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2017, Seoul, Republic of Korea, October 15-20, 2017. ACM 2017, ISBN 978-1-4503-5184-3
- Chaofan Li, Deepashree Sengupta, Farhana Sharmin Snigdha, Wenbin Xu, Jiang Hu, Sachin S. Sapatnekar
:
A quantifiable approach to approximate computing: special session. 1:1-1:2 - Majid Shoushtari, Amir M. Rahmani, Nikil D. Dutt:
Quality-configurable memory hierarchy through approximation: special session. 2:1-2:2 - Hassaan Saadat, Sri Parameswaran:
Hardware approximate computing: how, why, when and where? (special session). 3:1-3:2 - Sasa Misailovic:
Probabilistic reasoning for analysis of approximate computations. 4:1 - Wael M. Elsharkasy, Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi:
Efficient pulsed-latch implementation for multiport register files: work-in-progress. 5:1-5:2 - Xabier Iturbe, Balaji Venu, John Penton, Emre Ozer:
A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress. 6:1-6:2 - Sungin Hong, Hyunjun Kim, Hwansoo Han:
Balanced cache bypassing for critical warp reduction: work-in-progress. 7:1-7:2 - Gaoming Du, Shibi Ma, Zhenmin Li, Zhonghai Lu, Yiming Ouyang, Minglun Gao:
SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress). 8:1-8:2 - Mansureh S. Moghaddam, Barend Harris, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, Kiyoung Choi:
Incremental training of CNNs for user customization: work-in-progress. 9:1-9:2 - Yuan Yao, Zhonghai Lu:
Prediction based convolution neural network acceleration: work-in-progress. 10:1-10:2 - Hanwool Park, Changdae Lee, Hakkyung Lee, Yechan Yoo, Yoonjin Park, Injung Kim, Kang Yi:
Optimizing DCNN FPGA accelerator design for handwritten hangul character recognition: work-in-progress. 11:1-11:2 - Yuntao Lu, Lei Gong, Chongchong Xu, Fan Sun, Yiwei Zhang, Chao Wang, Xuehai Zhou:
A high-performance FPGA accelerator for sparse neural networks: work-in-progress. 12:1-12:2 - Mingze Ma, Rizos Sakellariou:
Code-size-aware mapping for synchronous dataflow graphs on multicore systems: work-in-progress. 13:1-13:2 - Miguel Angel Aguilar, Abhishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jerónimo Castrillón, Liam Fitzpatrick:
Multi-grained performance estimation for MPSoC compilers: work-in-progress. 14:1-14:2 - Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, François Neumann, Philippe Baufreton:
REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress). 15:1-15:2 - Hyukwoo Park, SungKook Kim, Soo-Mook Moon:
Advanced ahead-of-time compilation for Javascript engine: work-in-progress. 16:1-16:2 - Hussam Amrouch, Prashanth Krishnamurthy, Naman Patel, Jörg Henkel, Ramesh Karri, Farshad Khorrami:
Emerging (un-)reliability based security threats and mitigations for embedded systems: special session. 17:1-17:10 - Yaman Umuroglu, Magnus Jahre:
Towards efficient quantized neural network inference on mobile devices: work-in-progress. 18:1-18:2 - Seonbong Kim, Joon-Sung Yang:
Improving NVMe SSD I/O determinism with PCIe virtual channel: work-in-progress. 19:1-19:2 - Hao Yan, Ethan C. Ahn, Lide Duan:
Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress. 20:1-20:2 - Armin Haj Aboutalebi, Lide Duan:
Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress. 21:1-21:2 - Cosmin Avasalcai, Dhanesh Budhrani, Paul Pop:
Towards industry strength mapping of AUTOSAR automotive functionality on multicore architectures: work-in-progress. 22:1-22:2
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