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ORCIDIPSJ Transactions on System LSI Design Methodology, Volume 4
Volume 4, February 2011
- Hidetoshi Onodera:
Message from the Editor-in-Chief. 1 - Subhasish Mitra, Hyungmin Cho, Ted Hong, Young Moon Kim, Hsiao-Heng Lee, Larkhoon Leem, Yanjing Li, David Lin, Evelyn Mintarno, Diana Mui, Sung-Boem Park, Nishant Patil, Hai Wei, Jie Zhang:
Robust System Design. 2-30 - Kiyoung Choi:
Coarse-Grained Reconfigurable Array: Architecture and Application Mapping. 31-46 - Ryuta Nara, Nozomu Togawa
, Masao Yanagisawa, Tatsuo Ohtsuki:
Scan Vulnerability in Elliptic Curve Cryptosystems. 47-59 - Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. 60-69 - Hiroaki Yoshida, Masahiro Fujita:
Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability. 70-79 - Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. 80-90 - Philip Axer, Jonas Diemer, Mircea Negrean, Maurice Sebastian, Simon Schliecker, Rolf Ernst:
Mastering MPSoCs for Mixed-critical Applications. 91-116 - Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda:
Delay Testing: Improving Test Quality and Avoiding Over-testing. 117-130 - Hirotaka Kawashima, Naofumi Takagi:
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers. 131-139 - Kiyonori Matsumoto, Kazuteru Namba, Hideo Ito:
Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture. 140-149 - Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. 150-165 - Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. 166-181 - Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. 182-192 - Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan:
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. 193-209 - Yosuke Kakiuchi, Tomofumi Nakagawa, Kiyoharu Hamaguchi, Tadaaki Tanimoto, Masaki Nakanishi:
Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts. 210-221 - Arda Karaduman, Iver Stubdal, Hideharu Amano:
Design and Implementation of Echo Instructions for an Embedded Processor. 222-231 - Keisuke Inoue, Mineo Kaneko:
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. 232-244
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