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2010 – 2019
- 2012
[j39]Youhua Shi
, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 176-181 (2012)- 2011
- [j38]Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. Inf. Media Technol. 6(2): 276-285 (2011) - [j37]Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Inf. Media Technol. 6(4): 1076-1091 (2011) - [j36]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scan Vulnerability in Elliptic Curve Cryptosystems. IPSJ Trans. Syst. LSI Des. Methodol. 4: 47-59 (2011) - [j35]Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. IPSJ Trans. Syst. LSI Des. Methodol. 4: 60-69 (2011) - [j34]Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 4: 150-165 (2011) - [j33]Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 4: 166-181 (2011) - 2010
- [j32]Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2481-2489 (2010) - [j31]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1294-1299 (2010) - [c39]Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. APCCAS 2010: 712-715 - [c38]Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. APCCAS 2010: 1083-1086 - [c37]Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. APCCAS 2010: 1139-1142 - [c36]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scan-based attack against elliptic curve cryptosystems. ASP-DAC 2010: 407-412 - [c35]Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ISCAS 2010: 921-924 - [c34]Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS 2010: 1867-1870
2000 – 2009
- 2009
- [j30]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An L1 Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1442-1453 (2009) - [j29]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(9): 2304-2317 (2009) - [j28]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3119-3127 (2009) - [j27]Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3169-3179 (2009) - [j26]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Scan-Based Attack Based on Discriminators for AES Cryptosystems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3229-3237 (2009) - [j25]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Two-Level Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3238-3247 (2009) - [c33]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Exact and fast L1 cache simulation for embedded systems. ASP-DAC 2009: 817-822 - [c32]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Design-for-secure-test for crypto cores. ITC 2009: 1 - 2008
- [j24]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Trans. Inf. Syst. 91-D(3): 776-780 (2008) - [j23]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3514-3523 (2008) - [j22]Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. Inf. Media Technol. 3(4): 691-703 (2008) - [j21]Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 1: 78-90 (2008) - [c31]Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh:
FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm. APCCAS 2008: 701-704 - [c30]Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. APCCAS 2008: 705-708 - [c29]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Unknown response masking with minimized observable response loss and mask data. APCCAS 2008: 1779-1781 - [c28]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
GECOM: Test data compression combined with all unknown response masking. ASP-DAC 2008: 577-582 - [c27]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702 - 2007
- [c26]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS 2007: 149-152 - 2006
- [j20]Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. IEICE Trans. Electron. 89-C(3): 243-249 (2006) - [j19]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 996-1004 (2006) - [c25]Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC 2006: 594-599 - [c24]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC 2006: 653-658 - 2005
- [j18]Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 876-884 (2005) - [j17]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Trans. Inf. Syst. 88-D(7): 1340-1349 (2005) - [c23]Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A processor core synthesis system in IP-based SoC design. ASP-DAC 2005: 286-291 - [c22]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura:
Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium 2005: 386-389 - [c21]Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) 2005: 3499-3502 - 2004
- [c20]Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A thread partitioning algorithm in low power high-level synthesis. ASP-DAC 2004: 74-79 - [c19]Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC 2004: 250-255 - [c18]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC 2004: 743-750 - [c17]Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium 2004: 432-437 - 2003
- [j16]Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(5): 1082-1092 (2003) - [j15]Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3056-3062 (2003) - [j14]Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3099-3109 (2003) - [j13]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3218-3224 (2003) - [c16]Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A hardware/software partitioning algorithm for SIMD processor cores. ASP-DAC 2003: 135-140 - 2002
- [j12]Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 827-834 (2002) - [j11]Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2603-2611 (2002) - [j10]Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2655-2666 (2002) - [c15]Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) 2002: 171-176 - [c14]Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
VLSI Architecture for a Flexible Motion Estimation with Parameters. ASP-DAC/VLSI Design 2002: 452-457 - 2001
- [c13]Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Area/delay estimation for digital signal processor cores. ASP-DAC 2001: 156-161 - 2000
- [c12]Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki:
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). ASP-DAC 2000: 309-312
1990 – 1999
- 1999
- [j9]Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki:
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. J. Circuits Syst. Comput. 9(1-2): 09-112 (1999) - [j8]Tingrong Zhao, Masao Yanagisawa, Tatsuo Ohtsuki:
Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations. J. Circuits Syst. Comput. 9(1-2): 67-82 (1999) - [c11]Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ASP-DAC 1999: 335-338 - 1998
- [j7]Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 803-818 (1998) - [c10]Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki:
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. ASP-DAC 1998: 265-274 - [c9]Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki:
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. ASP-DAC 1998: 519-526 - 1997
- [j6]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems. J. Circuits Syst. Comput. 7(5): 373-394 (1997) - [c8]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. ASP-DAC 1997: 569-578 - 1995
- [c7]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. ASP-DAC 1995 - 1994
- [c6]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. ICCAD 1994: 156-163 - [c5]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A Simultaneous Placement and Global Routing Algorithm for FPGAs. ISCAS 1994: 483-486 - 1992
- [c4]Toru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki:
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion. ICCAD 1992: 162-165 - 1990
- [j5]Ernest S. Kuh, Tatsuo Ohtsuki:
Recent advances in VLSI layout. Proc. IEEE 78(2): 237-263 (1990) - [c3]Masao Sato, Kazuto Kubota, Tatsuo Ohtsuki:
A Hardware Implementation of Gridless Routing Based on Content Addressable Memory. DAC 1990: 646-649
1980 – 1989
- 1987
- [j4]Masao Sato, Tatsuo Ohtsuki:
Applications of computational geometry to VLSI layout pattern design. Integr. 5(3-4): 303-317 (1987) - 1986
- [j3]Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki:
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4): 466-476 (1986) - 1981
- [j2]Tatsuo Ohtsuki, Hajimu Mori, Toshinobu Kashiwabara, Toshio Fujisawa:
On Minimal Augmentation of a Graph to Obtain an Interval Graph. J. Comput. Syst. Sci. 22(1): 60-97 (1981) - 1980
- [c2]Tatsuo Ohtsuki:
The two disjoint path problem and wire routing design. Graph Theory and Algorithms 1980: 207-216
1970 – 1979
- 1979
- [c1]Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa:
One-dimensional logic gate assignment and interval graphs. COMPSAC 1979: 101-106 - 1976
- [j1]Tatsuo Ohtsuki:
A Fast Algorithm for Finding an Optimal Ordering for Vertex Elimination on a Graph. SIAM J. Comput. 5(1): 133-145 (1976)
Coauthor Index
[j39] [j38] [j37] [j36] [j35] [j34] [j33] [j32] [j31] [c39] [c38] [c37] [c36] [c35] [c34] [j30] [j29] [j28] [j27] [j26] [j25] [c33] [c32] [j24] [j23] [j22] [j21] [c31] [c30] [c29] [c28] [c27] [c26] [j20] [j19] [c25] [c24] [j18] [j17] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [j16] [j14] [j13] [c16] [j12] [j11] [j10] [c15] [c14] [c13] [c12] [j9] [c11] [j7] [c10] [c9] [j6] [c8] [c7] [c6] [c5]
[j39] [j38] [j37] [j36] [j35] [j34] [j33] [j32] [j31] [c39] [c38] [c37] [c36] [c35] [c34] [j30] [j29] [j28] [j27] [j26] [j25] [c33] [c32] [j24] [j23] [j22] [j21] [c31] [c30] [c29] [c28] [c27] [c26] [j20] [j19] [c25] [c24] [j18] [j17] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [j16] [j15] [j14] [j13] [c16] [j12] [j11] [j10] [c15] [c14] [c13] [c12] [j9] [j8] [c11] [j7] [c10] [c9]
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