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ORCIDToshinobu Kashiwabara
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2010 – 2019
- 2010
[j14]Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara:
Approximate Model Checking Using a Subset of First-order Logic. Inf. Media Technol. 5(4): 1132-1146 (2010)- [j13]Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. IPSJ Trans. Syst. LSI Des. Methodol. 3: 105-117 (2010) - [j12]Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara:
Approximate Model Checking Using a Subset of First-order Logic. IPSJ Trans. Syst. LSI Des. Methodol. 3: 268-282 (2010)
2000 – 2009
- 2009
- [j11]Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Checker Generation of Assertions with Local Variables for Model Checking. Inf. Media Technol. 4(2): 227-239 (2009) - [j10]Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Checker Generation of Assertions with Local Variables for Model Checking. IPSJ Trans. Syst. LSI Des. Methodol. 2: 80-92 (2009) - 2008
- [c7]Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. ATVA 2008: 318-331 - 2007
- [j9]Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2778-2789 (2007) - 2006
- [j8]Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Expressive Power of Quantum Pushdown Automata with Classical Stack Operations under the Perfect-Soundness Condition. IEICE Trans. Inf. Syst. 89-D(3): 1120-1127 (2006) - 2005
- [c6]Yosuke Kakiuchi, A. Kitajima, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Automatic monitor generation from regular expression based specifications for module interface verification. ISCAS (4) 2005: 3555-3558 - 2004
- [c5]Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas. ATVA 2004: 108-119 - 2002
- [j7]Masakuni Taki, Mikihito Sugiura, Toshinobu Kashiwabara:
On-Line Edge-Coloring Algorithms for Degree-Bounded Bipartite Graphs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(5): 1062-1065 (2002) - 2000
- [c4]Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction. COCOON 2000: 467-476 - [c3]Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara:
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs. FMCAD 2000: 455-469
1990 – 1999
- 1992
- [j6]Toshinobu Kashiwabara, Sumio Masuda, Kazuo Nakajima, Toshio Fujisawa:
Generation of Maximum Independent Sets of a Bipartite Graph and Maximum Cliques of a Circular-Arc Graph. J. Algorithms 13(1): 161-174 (1992) - 1991
- [j5]Toshinobu Kashiwabara, Sumio Masuda, Kazuo Nakajima, Toshio Fujisawa:
Polynomial time algorithms on circular-arc overlap graphs. Networks 21(2): 195-203 (1991) - 1990
- [j4]Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa:
Efficient algorithms for finding maximum cliques of an overlap graph. Networks 20(2): 157-171 (1990) - [j3]Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa:
Crossing Minimization in Linear Embeddings of Graphs. IEEE Trans. Computers 39(1): 124-127 (1990)
1980 – 1989
- 1989
- [j2]Chong S. Rim, Toshinobu Kashiwabara, Kazuo Nakajima:
Exact algorithms for multilayer topological via minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(11): 1165-1173 (1989) - 1981
- [j1]Tatsuo Ohtsuki, Hajimu Mori, Toshinobu Kashiwabara, Toshio Fujisawa:
On Minimal Augmentation of a Graph to Obtain an Interval Graph. J. Comput. Syst. Sci. 22(1): 60-97 (1981) - 1980
- [c2]Toshinobu Kashiwabara:
Algorithms for some intersection graphs. Graph Theory and Algorithms 1980: 171-181
1970 – 1979
- 1979
- [c1]Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa:
One-dimensional logic gate assignment and interval graphs. COMPSAC 1979: 101-106
Coauthor Index
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