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ORCIDIntegration, Volume 5
Volume 5, Number 1, March 1987
- Lambert Spaanenburg:
Editorial. 1 - Eugene Shragowitz, S. Keel:
A global router based on a multicommodity flow model. 3-16 - H. W. Leong, C. L. Liu:
Algorithms for permutation channel routing. 17-45 - A. S. Shubat, J. A. Pretorias, C. André T. Salama:
Expandable arithmetic block macrocell. 47-71 - Tao Li:
SYSIM: a simulation tool for systolic processors. 73-76 - Bruno Codenotti, Francesco Romani
:
A compact and modular VLSI design for the solution of general sparse linear systems. 77-86
Volume 5, Number 2, June 1987
- Lambert Spaanenburg:
Editorial. 101 - Janusz A. Brzozowski, Michael Yoeli:
Combinational static CMOS networks. 103-122 - Christer Svensson:
Guest editorial. 123 - Mark R. Greenstreet, Peter Møller-Nielsen, Jørgen Staunstrup:
VLSI with a very low scale investment. 125-132 - Krzysztof Kuchcinski, Zebo Peng:
Microprogramming implementation of timed Petri nets. 133-144 - Tony Larsson:
Semantics of a hardware specification language and related transformation rules. 145-158 - B. Sikström, Lars Wanhammar, Morteza Afghahi, J. Pencz:
A high speed 2-D discrete cosine transform chip. 159-169 - Olli Vainio, Pekka Heinonen, Yrjö Neuvo:
Integrated FIR median hybrid filter. 171-177
Volume 5, Numbers 3-4, December 1987
- Lambert Spaanenburg:
Editorial. 191 - Daniele D. Caviglia, Vincenzo Piuri, Mauro Santomauro:
About folded-PLA area and folding evaluation. 193-215 - Yue-Sun Kuo, T. C. Hu:
An effective algorithm for optimal PLA column folding. 217-230 - Majid Sarrafzadeh, Franco P. Preparata:
A bottom-up layout technique based on two-rectangle routing. 231-246 - Howard C. Card:
VLSI computations: from physics to algorithms. 247-273 - Steven E. Butner:
Evaluation of a prototype VLSI tester. 275-288 - O. P. Traynor, Jon R. Malone:
Design rule checking and VLSI. 289-302 - Masao Sato, Tatsuo Ohtsuki:
Applications of computational geometry to VLSI layout pattern design. 303-317 - Nils Hedenstierna, Kjell O. Jeppson:
New algorithms for increased efficiency in hierarchical design rule checking. 319-336
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