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2010 – 2019
- 2016
[j35]Xin Yuan, Takanori Yazawa, Hideo Ito, Tatsuki Otsubo, Yukio Maeda, Reiko Yamada:
High-Efficiency Milling of Steam Turbine Blade. Int. J. Autom. Technol. 10(6): 993-999 (2016)- 2014
- [j34]Wenpo Zhang, Kazuteru Namba, Hideo Ito:
Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement. IEICE Trans. Inf. Syst. 97-D(3): 533-540 (2014) - [j33]Wenpo Zhang, Kazuteru Namba, Hideo Ito:
Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion. IEICE Trans. Inf. Syst. 97-D(10): 2719-2729 (2014) - 2013
- [j32]Kazuteru Namba, Takashi Katagiri, Hideo Ito:
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop. J. Electron. Test. 29(4): 545-554 (2013) - [j31]Wenpo Zhang, Kazuteru Namba, Hideo Ito:
Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF. IEICE Trans. Inf. Syst. 96-D(5): 1219-1222 (2013) - [j30]Kazuteru Namba, Nobuhide Takashina, Hideo Ito:
Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA. IEICE Trans. Inf. Syst. 96-D(8): 1613-1623 (2013) - 2012
- [j29]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 804-817 (2012) - [c42]Kazuteru Namba, Takashi Katagiri, Hideo Ito:
Dual-edge-triggered FF with timing error detection capability. DFT 2012: 187-192 - [c41]Wenpo Zhang, Kazuteru Namba, Hideo Ito:
Improving small-delay fault coverage for on-chip delay measurement. DFT 2012: 193-198 - 2011
- [j28]Kazuteru Namba, Hideo Ito:
Construction of BILBO FF with Soft-Error-Tolerant Capability. IEICE Trans. Inf. Syst. 94-D(5): 1045-1050 (2011) - [j27]Kiyonori Matsumoto, Kazuteru Namba, Hideo Ito:
Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 4: 140-149 (2011) - [j26]Kazuteru Namba, Hideo Ito:
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. IEEE Trans. Computers 60(10): 1459-1470 (2011) - 2010
- [j25]Kazuteru Namba, Hideo Ito:
Chiba Scan Delay Fault Testing with Short Test Application Time. J. Electron. Test. 26(6): 667-677 (2010) - [j24]Kazuteru Namba, Kengo Nakashima, Hideo Ito:
Single-Event-Upset Tolerant RS Flip-Flop with Small Area. IEICE Trans. Inf. Syst. 93-D(12): 3407-3409 (2010) - [j23]Kazuteru Namba, Takashi Ikeda, Hideo Ito:
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1265-1276 (2010) - [c40]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. Asian Test Symposium 2010: 343-348 - [c39]Kazuteru Namba, Hideo Ito:
Soft Error Tolerant BILBO FF. DFT 2010: 73-81 - [c38]Kazuteru Namba, Masatoshi Sakata, Hideo Ito:
Single Event Induced Double Node Upset Tolerant Latch. DFT 2010: 280-288 - [c37]Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito:
Quantitative Evaluation of Integrity for Remote System Using the Internet. PRDC 2010: 229-230
2000 – 2009
- 2009
- [j22]Kazuteru Namba, Yoshikazu Matsui, Hideo Ito:
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. J. Electron. Test. 25(1): 97-105 (2009) - [j21]Kazuteru Namba, Hideo Ito:
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding. IEICE Trans. Inf. Syst. 92-D(2): 269-282 (2009) - [j20]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Trans. Inf. Syst. 92-D(2): 336-341 (2009) - [j19]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Trans. Inf. Syst. 92-D(3): 433-442 (2009) - [j18]Shuangyu Ruan, Kazuteru Namba, Hideo Ito:
Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability. IEICE Trans. Inf. Syst. 92-D(8): 1534-1541 (2009) - [j17]Kazuteru Namba, Hideo Ito:
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(9): 2295-2303 (2009) - [c36]Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito:
A Delay Measurement Technique Using Signature Registers. Asian Test Symposium 2009: 157-162 - [c35]Takumi Hoshi, Kazuteru Namba, Hideo Ito:
Testing of Switch Blocks in Three-Dimensional FPGA. DFT 2009: 227-235 - [c34]Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito:
Dependability Evaluation for Internet-Based Remote Systems. PRDC 2009: 256-259 - 2008
- [j16]Yoichi Sasaki, Kazuteru Namba, Hideo Ito:
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. J. Electron. Test. 24(1-3): 11-19 (2008) - [j15]Masato Kitakami, Bochuan Cai, Hideo Ito:
A Checkpointing Method with Small Checkpoint Latency. IEICE Trans. Inf. Syst. 91-D(3): 857-861 (2008) - [j14]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. Inf. Media Technol. 3(4): 704-716 (2008) - [j13]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. IPSJ Trans. Syst. LSI Des. Methodol. 1: 91-103 (2008) - [j12]Toshinori Takabatake, Tomoki Nakamigawa, Hideo Ito:
Connectivity of Generalized Hierarchical Completely-Connected Networks. J. Interconnect. Networks 9(1/2): 127-139 (2008) - [c33]Shuangyu Ruan, Kazuteru Namba, Hideo Ito:
Soft Error Hardened FF Capable of Detecting Wide Error Pulse. DFT 2008: 272-280 - [c32]Kazuteru Namba, Hideo Ito:
Delay Fault Testability on Two-Rail Logic Circuits. DFT 2008: 482-490 - [c31]Kazuteru Namba, Hideo Ito:
Path Delay Fault Test Set for Two-Rail Logic Circuits. PRDC 2008: 347-348 - 2007
- [j11]Gang Zeng, Hideo Ito:
Low-Cost IP Core Test Using Tri-Template-Based Codes. IEICE Trans. Inf. Syst. 90-D(1): 288-295 (2007) - [c30]Abderrahim Doumar, Kentaroh Katoh, Hideo Ito:
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. DFT 2007: 31-40 - [c29]Takashi Ikeda, Kazuteru Namba, Hideo Ito:
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. DFT 2007: 282-290 - 2006
- [j10]Gang Zeng, Hideo Ito:
Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree. IEICE Trans. Inf. Syst. 89-D(3): 1157-1164 (2006) - [j9]Kazuteru Namba, Hideo Ito:
Proposal of Testable Multi-Context FPGA Architecture. IEICE Trans. Inf. Syst. 89-D(5): 1687-1693 (2006) - [j8]Kazuteru Namba, Hideo Ito:
Redundant Design for Wallace Multiplier. IEICE Trans. Inf. Syst. 89-D(9): 2512-2524 (2006) - [c28]Kazuteru Namba, Hideo Ito:
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding. ATS 2006: 389-394 - [c27]Gang Zeng, Hideo Ito:
Concurrent core test for SOC using shared test set and scan chain disable. DATE 2006: 1045-1050 - [c26]Gang Zeng, Youhua Shi
, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito:
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT 2006: 136-144 - [c25]Yoichi Sasaki, Kazuteru Namba, Hideo Ito:
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. DFT 2006: 327-335 - [c24]Kentaroh Katoh, Hideo Ito:
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. ETS 2006: 69-74 - 2005
- [j7]Gang Zeng, Hideo Ito:
Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core. IEICE Trans. Inf. Syst. 88-D(5): 984-992 (2005) - [j6]Gang Zeng, Hideo Ito:
X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability. IEICE Trans. Inf. Syst. 88-D(7): 1662-1670 (2005) - [j5]Kazuteru Namba, Hideo Ito:
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. IEICE Trans. Inf. Syst. 88-D(9): 2135-2142 (2005) - [j4]Kazuteru Namba, Hideo Ito:
Scan Design for Two-Pattern Test without Extra Latches. IEICE Trans. Inf. Syst. 88-D(12): 2777-2785 (2005) - [c23]Gang Zeng, Hideo Ito:
Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. ICCD 2005: 143-146 - [c22]Kentaroh Katoh, Abderrahim Doumar, Hideo Ito:
Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. IOLTS 2005: 203-204 - [c21]Kazuteru Namba, Hideo Ito:
Design of Defect Tolerant Wallace Multiplier. PRDC 2005: 300-304 - 2004
- [c20]Gang Zeng, Hideo Ito:
Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. DFT 2004: 413-421 - [c19]Manabu Sueishi, Masato Kitakami, Hideo Ito:
Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking. PRDC 2004: 183-190 - [c18]Gang Zeng, Hideo Ito:
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. VTS 2004: 355-360 - 2003
- [j3]Abderrahim Doumar, Hideo Ito:
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 386-405 (2003) - [c17]Gang Zeng, Hideo Ito:
Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. DFT 2003: 503-510 - 2002
- [c16]Lihong Tong, Kazuki Suzuki, Hideo Ito:
Optimal Seed Generation for Delay Fault Detection BIST. Asian Test Symposium 2002: 116-121 - [c15]Toshinori Takabatake, Masato Kitakami, Hideo Ito:
A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks. IASTED PDCS 2002: 619-624 - [c14]Toshinori Takabatake, Masato Kitakami, Hideo Ito:
Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks. PRDC 2002: 137-144 - 2001
- [c13]Toshinori Takabatake, Masato Kitakami, Hideo Ito:
Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks. PRDC 2001: 127-136 - [c12]Masato Kitakami, Shunji Kubota, Hideo Ito:
Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction. PRDC 2001: 319-324 - 2000
- [c11]Abderrahim Doumar, Hideo Ito:
Testing approach within FPGA-based fault tolerant systems. Asian Test Symposium 2000: 411-416 - [c10]Abderrahim Doumar, Hideo Ito:
Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. DFT 2000: 134-142
1990 – 1999
- 1999
- [c9]Abderrahim Doumar, Hideo Ito:
Testing the Logic Cells and Interconnect Resources for FPGAs. Asian Test Symposium 1999: 369-374 - [c8]Abderrahim Doumar, Satoshi Kaneko, Hideo Ito:
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. DFT 1999: 377-385 - [c7]Abderrahim Doumar, Toshiaki Ohmameuda, Hideo Ito:
Design of an automatic testing for FPGAs. ETW 1999: 152-157 - [c6]Keiichi Kaneko, Hideo Ito:
Fault-Tolerant Routing Algorithms for Hypercube Networks. IPPS/SPDP 1999: 218-224 - [c5]Toshinori Takabatake, Keiichi Kaneko, Hideo Ito:
Generalized Hierarchical Completely-Connected Networks. ISPAN 1999: 68-73 - [c4]Mikio Yagi, Keiichi Kaneko, Hideo Ito:
LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments. PRDC 1999: 23- - [c3]Abderrahim Doumar, Hideo Ito:
An Automatic Testing and Diagnosis for FPGAs. PRDC 1999: 45- - 1998
- [j2]Hammadi Nait-Charif, Hideo Ito:
Improving the Performance of Feedforward Neural Networks by Noise Injection into Hidden Neurons. J. Intell. Robotic Syst. 21(2): 103-115 (1998) - 1994
- [c2]Hideo Ito, Takashi Yagi:
Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. DFT 1994: 177-184 - 1993
- [c1]Hideo Ito:
A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. DFT 1993: 80-87 - 1991
- [j1]Hideo Ito, Nobuyuki Suzuki:
A hypercube design on wafer-scale integration. Syst. Comput. Jpn. 22(4): 29-40 (1991)
Coauthor Index
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