"Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits."

Kazuteru Namba, Hideo Ito (2009)

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DOI: 10.1587/TRANSFUN.E92.A.2295

access: closed

type: Journal Article

metadata version: 2020-04-11

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Kazuteru Namba, Hideo Ito:
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(9): 2295-2303 (2009)

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