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ORCIDKentaroh Katoh
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2020 – today
- 2023
[j10]Shogo Katayama, Takayuki Nakatani, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi:
Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing. IEICE Electron. Express 20(1): 20220470 (2023)- [c12]Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi:
Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. ITC 2023: 47-55 - [c11]Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation. ITC-Asia 2023: 1-6 - 2022
- [j9]Yujie Zhao
, Kentaroh Katoh, Anna Kuwana, Shogo Katayama, Jianglin Wei, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies. J. Electron. Test. 38(1): 21-38 (2022) - [c10]Keno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST. ATS 2022: 37-42 - [c9]Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS 2022: 1
2010 – 2019
- 2015
- [j8]Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi:
Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. J. Electron. Test. 31(4): 419 (2015) - [c8]Kentaroh Katoh, Kazuteru Namba:
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement. ISQED 2015: 430-434 - 2014
- [j7]Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi:
A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. J. Electron. Test. 30(6): 653-663 (2014) - [j6]Haruo Kobayashi, Hitoshi Aoki, Kentaroh Katoh, Congbing Li:
Analog/mixed-signal circuit design in nano CMOS era. IEICE Electron. Express 11(3): 20142001 (2014) - 2013
- [c7]Ru Yi, Minghui Wu, Koji Asami, Haruo Kobayashi, Ramin Khatami, Atsuhiro Katayama, Isao Shimizu, Kentaroh Katoh:
Digital Compensation for Timing Mismatches in Interleaved ADCs. Asian Test Symposium 2013: 134-139 - [c6]Kentaroh Katoh, Yuta Doi, Satoshi Ito, Haruo Kobayashi, Ensi Li, Nobukazu Takai:
An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators. Asian Test Symposium 2013: 140-146 - 2012
- [j5]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 804-817 (2012) - 2010
- [c5]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. Asian Test Symposium 2010: 343-348
2000 – 2009
- 2009
- [j4]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Trans. Inf. Syst. 92-D(2): 336-341 (2009) - [j3]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Trans. Inf. Syst. 92-D(3): 433-442 (2009) - [c4]Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito:
A Delay Measurement Technique Using Signature Registers. Asian Test Symposium 2009: 157-162 - 2008
- [j2]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. Inf. Media Technol. 3(4): 704-716 (2008) - [j1]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. IPSJ Trans. Syst. LSI Des. Methodol. 1: 91-103 (2008) - 2007
- [c3]Abderrahim Doumar, Kentaroh Katoh, Hideo Ito:
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. DFT 2007: 31-40 - 2006
- [c2]Kentaroh Katoh, Hideo Ito:
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. ETS 2006: 69-74 - 2005
- [c1]Kentaroh Katoh, Abderrahim Doumar, Hideo Ito:
Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. IOLTS 2005: 203-204
Coauthor Index
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