"Design for Delay Fault Testability of 2-Rail Logic Circuits."

Kentaroh Katoh, Kazuteru Namba, Hideo Ito (2009)

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DOI: 10.1587/TRANSINF.E92.D.336

access: closed

type: Journal Article

metadata version: 2020-04-11

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Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Trans. Inf. Syst. 92-D(2): 336-341 (2009)

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