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Debabrata Ghosh
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2020 – today
- 2025
- [j10]Prakash Awasthy, Tanushree Haldar, Debabrata Ghosh:
Blockchain enabled traceability - An analysis of pricing and traceability effort decisions in supply chains. Eur. J. Oper. Res. 321(3): 760-774 (2025) - 2024
- [j9]Debabrata Ghosh, Kuntal Chowdhury, Samya Muhuri:
Finding correlation between diabetic retinopathy and diabetes during pregnancy based on computer-aided diagnosis: a review. Multim. Tools Appl. 83(9): 27037-27065 (2024) - 2023
- [c16]Puviyarasi Thirugnanasammandamoorthi, Debabrata Ghosh, Ram Kishan Dewangan:
Uncovering the Extent of Flood Damage using Sentinel-1 SAR Imagery: A Case Study of the July 2020 Flood in Assam. CVIP (2) 2023: 102-114 - 2020
- [j8]Debabrata Ghosh, Janat Shah, Sanjeev Swami:
Product greening and pricing strategies of firms under green sensitive consumer demand and environmental regulations. Ann. Oper. Res. 290(1): 491-520 (2020)
2010 – 2019
- 2019
- [j7]Vaishnavi Tunuguntla, Preetam Basu, Krishanu Rakshit, Debabrata Ghosh:
Sponsored search advertising and dynamic pricing for perishable products under inventory-linked customer willingness to pay. Eur. J. Oper. Res. 276(1): 119-132 (2019) - [j6]Mithu Rani Kuiti, Debabrata Ghosh, Sirish Kumar Gouda, Sanjeev Swami, Ravi Shankar:
Integrated product design, shelf-space allocation and transportation decisions in green supply chains. Int. J. Prod. Res. 57(19): 6181-6201 (2019) - 2016
- [j5]Debabrata Ghosh, Naima Kaabouch:
A survey on image mosaicing techniques. J. Vis. Commun. Image Represent. 34: 1-11 (2016) - [j4]Debabrata Ghosh, Naima Kaabouch, Wen-Chen Hu:
A robust iterative super-resolution mosaicking algorithm using an adaptive and directional Huber-Markov regularization. J. Vis. Commun. Image Represent. 40: 98-110 (2016) - 2014
- [j3]Debabrata Ghosh, Naima Kaabouch, Ronald A. Fevig:
Robust Spatial-Domain Based Super-Resolution Mosaicing of CubeSat Video Frames: Algorithm and Evaluation. Comput. Inf. Sci. 7(2): 68-81 (2014) - 2013
- [c15]Debabrata Ghosh, Ramasamy Subramanian, Vinay Murthy:
A randomized methodology for post-silicon validation of CAN and other communication modules. ICACCI 2013: 886-890 - 2012
- [c14]Sangho Park, Debabrata Ghosh, Naima Kaabouch, Ronald A. Fevig, William Semke:
Hierarchical multi-level image mosaicing for autonomous navigation of UAV. Intelligent Robots and Computer Vision: Algorithms and Techniques 2012: 830116 - [c13]Debabrata Ghosh, Sangho Park, Naima Kaabouch, William Semke:
Quantitative evaluation of image mosaicing in multiple scene categories. EIT 2012: 1-6 - 2011
- [c12]Ashish M. Gujarathi, Saumitra Purohit, Rohan Manchanda, Debabrata Ghosh:
Differential Evolution using Jumping Genes Adaptation. IICAI 2011: 353-370
2000 – 2009
- 2001
- [j2]Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh:
Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization. ACM J. Exp. Algorithmics 6: 8 (2001)
1990 – 1999
- 1999
- [c11]Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh:
Heuristics and Experimental Design for Bigraph Crossing Number Minimization. ALENEX 1999: 74-93 - [c10]Debabrata Ghosh, Franc Brglez:
Equivalence classes of circuit mutants for experimental design. ISCAS (6) 1999: 432-435 - [c9]Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh:
Evaluating iterative improvement heuristics for bigraph crossing minimization. ISCAS (6) 1999: 444-447 - 1998
- [c8]Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III:
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. DATE 1998: 656-663 - 1997
- [c7]Nevin Kapur, Debabrata Ghosh, Franc Brglez:
Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. ISPD 1997: 136-143 - 1995
- [j1]Debabrata Ghosh, S. K. Nandy:
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 36-48 (1995) - [c6]Debabrata Ghosh, Soumitra Kumar Nandy:
Wave pipelined architecture folding: a method to achieve low power and low area. VLSI Design 1995: 184- - 1994
- [c5]Debabrata Ghosh, S. K. Nandy, K. Parthasarathy:
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. VLSI Design 1994: 77-82 - [c4]Debabrata Ghosh, Shamik Sural, S. K. Nandy:
A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. VLSI Design 1994: 95-100 - 1993
- [c3]Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy:
Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. DAC 1993: 303-307 - [c2]Debabrata Ghosh, S. K. Nandy:
A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. ICCD 1993: 198-201 - [c1]Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan:
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. VLSI Design 1993: 341-346
Coauthor Index
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