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2010 – 2019
- 2011
[j1]Markus Rullmann, Renate Merker:
A Cost Model for Partial Dynamic Reconfiguration. Trans. High Perform. Embed. Archit. Compil. 4: 370-390 (2011)- 2010
- [p1]Markus Rullmann, Renate Merker:
Design Methods and Tools for Improved Partial Dynamic Reconfiguration. Dynamically Reconfigurable Systems 2010: 161-181
2000 – 2009
- 2009
- [c9]Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf
, Manfred Glesner:
An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. FPL 2009: 92-98 - 2008
- [c8]Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker:
Fine grain reconfigurable architectures. FPL 2008: 348 - [c7]Markus Rullmann, Renate Merker:
Synthesis of efficiently reconfigurable datapaths for reconfigurable computing. FPT 2008: 277-280 - [c6]Markus Rullmann, Renate Merker:
A cost model for partial dynamic reconfiguration. ICSAMOS 2008: 182-186 - 2007
- [c5]Markus Rullmann, Renate Merker:
A Reconfiguration Aware Circuit Mapper for FPGAs. IPDPS 2007: 1-8 - 2006
- [c4]Markus Rullmann, Renate Merker:
Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead. ARCS Workshops 2006: 132-141 - [c3]Markus Rullmann, Renate Merker:
Maximum edge matching for reconfigurable computing. IPDPS 2006 - 2005
- [c2]Markus Rullmann, Sebastian Siegel, Renate Merker:
Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching. IPDPS 2005 - 2003
- [c1]Markus Rullmann, Jens-Uwe Schluessler, René Schüffny:
On-chip digital noise reduction for integrated CMOS Cameras. VCIP 2003: 1620-1629
Coauthor Index
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