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ORCIDSebastian Siegel
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2020 – today
- 2024
[c12]Zhenming Yu, Ming-Jay Yang, Jan Finkbeiner, Sebastian Siegel, John Paul Strachan, Emre Neftci:
The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming. AICAS 2024: 398-402- [i5]Zhenming Yu, Ming-Jay Yang, Jan Finkbeiner, Sebastian Siegel, John Paul Strachan, Emre Neftci:
The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming. CoRR abs/2403.06712 (2024) - [i4]Tyler Hennen, Leon Brackmann, Tobias Ziegler, Sebastian Siegel, Stephan Menzel, Rainer Waser, Dirk J. Wouters, Daniel Bedau:
Synaptogen: A cross-domain generative device model for large-scale neuromorphic circuit design. CoRR abs/2404.06344 (2024) - [i3]Nathan Leroux, Paul-Philipp Manea, Chirag Sudarshan, Jan Finkbeiner, Sebastian Siegel, John Paul Strachan, Emre Neftci:
Analog In-Memory Computing Attention Mechanism for Fast and Energy-Efficient Large Language Models. CoRR abs/2409.19315 (2024) - 2023
- [j2]Sebastian Siegel
, Younes Bouhadjar, Tom Tetzlaff, Rainer Waser, Regina Dittmann, Dirk J. Wouters:
System model of neuromorphic sequence learning on a memristive crossbar array. Neuromorph. Comput. Eng. 3(2): 24002 (2023) - [j1]Younes Bouhadjar, Sebastian Siegel, Tom Tetzlaff, Markus Diesmann, Rainer Waser, Dirk J. Wouters:
Sequence learning in a spiking neuronal network with memristive synapses. Neuromorph. Comput. Eng. 3(3): 34014 (2023) - [c11]Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers:
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CODES+ISSS 2023: 44-45 - [c10]Sebastian Siegel, Tobias Ziegler, Younes Bouhadjar, Tom Tetzlaff, Rainer Waser, Regina Dittmann, Dirk J. Wouters:
Demonstration of neuromorphic sequence learning on a memristive array. NICE 2023: 108-114 - [i2]Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers:
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CoRR abs/2308.02400 (2023) - 2022
- [i1]Younes Bouhadjar, Sebastian Siegel, Tom Tetzlaff, Markus Diesmann, Rainer Waser, Dirk J. Wouters:
Sequence learning in a spiking neuronal network with memristive synapses. CoRR abs/2211.16592 (2022)
2000 – 2009
- 2007
- [b1]Sebastian Siegel:
Abbildungsverfahren zur effizienten Implementierung rechenintensiver Algorithmen auf Prozessorarrays. Dresden University of Technology, Germany, 2007, ISBN 978-3-8325-2666-5, pp. 1-153 - [c9]Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68 - 2006
- [c8]Sebastian Siegel, Renate Merker:
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy. ASAP 2006: 28-32 - [c7]Sebastian Siegel, Renate Merker:
Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints. Euro-Par 2006: 1181-1191 - [c6]Sebastian Siegel, Rainer Schaffer, Renate Merker:
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels. PARELEC 2006: 173-180 - 2005
- [c5]Markus Rullmann, Sebastian Siegel, Renate Merker:
Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching. IPDPS 2005 - [c4]Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34 - 2004
- [c3]Sebastian Siegel, Renate Merker:
Optimized Data-Reuse in Processor Arrays. ASAP 2004: 315-325 - [c2]Sebastian Siegel, Renate Merker:
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays. PARELEC 2004: 85-90 - [c1]Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber:
A Parallel Hardware-Software System for Signal Processing Algorithms. PARELEC 2004: 215-220
Coauthor Index
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