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2010 – 2019
- 2012
[c13]Falko Guderian, Rainer Schaffer, Gerhard P. Fettweis:
Administration- and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing. IEEE Congress on Evolutionary Computation 2012: 1-8- [c12]Falko Guderian, Rainer Schaffer, Gerhard P. Fettweis:
Dimensioning the heterogeneous multicluster architecture via parallelism analysis and evolutionary computing. IEEE Congress on Evolutionary Computation 2012: 1-8 - 2010
- [b1]Rainer Schaffer:
Parallelisierung von Algorithmen zur Nutzung auf Architekturen mit Teilwortparallelität. Dresden University of Technology, Vogt 2010, ISBN 978-3-938860-37-3, pp. 1-250
2000 – 2009
- 2008
- [c11]Rainer Schaffer, Renate Merker, Frank Hannig
, Jürgen Teich:
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD 2008: 391-398 - 2007
- [c10]Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68 - 2006
- [c9]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker:
An Architecture Description Language for Massively Parallel Processor Architectures. MBMV 2006: 11-20 - [c8]Rainer Schaffer, Renate Merker, Francky Catthoor:
Derivation of Packing Instructions for Exploiting Sub-Word Parallelism. PARELEC 2006: 167-172 - [c7]Sebastian Siegel, Rainer Schaffer, Renate Merker:
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels. PARELEC 2006: 173-180 - [c6]Rainer Schaffer, Renate Merker:
Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism. ICSAMOS 2006: 99-106 - 2005
- [c5]Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34 - 2004
- [c4]Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber:
A Parallel Hardware-Software System for Signal Processing Algorithms. PARELEC 2004: 215-220 - 2003
- [j2]Jan Müller, Dirk Fimmel, Renate Merker, Rainer Schaffer:
A Hardware-Software System for Tomographic Reconstruction. J. Circuits Syst. Comput. 12(2): 203- (2003) - [c3]Rainer Schaffer, Renate Merker, Francky Catthoor:
Causality Constraints for Processor Architectures with Sub-Word Parallelism. DSD 2003: 82-89 - 2002
- [c2]Rainer Schaffer, Renate Merker, Francky Catthoor:
Systematic Design of Programs with Sub-Word Parallelism. PARELEC 2002: 393-398 - 2000
- [j1]Rainer Schaffer, Francky Catthoor, Renate Merker:
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. Parallel Algorithms Appl. 15(3-4): 201-228 (2000) - [c1]Rainer Schaffer, Renate Merker, Francky Catthoor:
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. VLSI Design 2000: 104-109
Coauthor Index
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