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2010 – 2019
- 2011
[b1]Mateusz Majer:
The Erlangen Slot Machine - An FPGA-Based Partially Reconfigurable Computer. University of Erlangen-Nuremberg, 2011- 2010
- [p2]Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich:
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform. Dynamically Reconfigurable Systems 2010: 51-71 - [p1]Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen:
ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices. Dynamically Reconfigurable Systems 2010: 199-221
2000 – 2009
- 2008
- [j3]Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich:
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1210-1219 (2008) - [c17]Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele:
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC 2008: 148-158 - [c16]Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner
, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker:
Fine grain reconfigurable architectures. FPL 2008: 348 - [c15]Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich:
Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. IEEE International Workshop on Rapid System Prototyping 2008: 142-148 - 2007
- [j2]Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens). it Inf. Technol. 49(3): 143- (2007) - [j1]Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda:
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. J. VLSI Signal Process. 47(1): 15-31 (2007) - 2006
- [c14]Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich:
A Flexible Reconfiguration Manager for the Erlangen Slot Machine. ARCS Workshops 2006: 183-194 - [c13]Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich:
Minimizing Communication Cost for Reconfigurable Slot Modules. FPL 2006: 1-6 - [c12]Mateusz Majer:
An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization. FPL 2006: 1-2 - [i3]Diana Göhringer, Mateusz Majer, Jürgen Teich:
Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. Dynamically Reconfigurable Architectures 2006 - 2005
- [c11]Christophe Bobda, Ali Ahmadinia, Kurapati Rajesham, Mateusz Majer, Adronis Niyonkuru:
Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs. ARCS Workshops 2005: 61-66 - [c10]Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich:
Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104 - [c9]Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. FCCM 2005: 319-320 - [c8]Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. FPL 2005: 153-158 - [c7]Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich:
The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. FPT 2005: 37-42 - [c6]Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich:
Packet Routing in Dynamically Changing Networks on Chip. IPDPS 2005 - [c5]Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. IEEE International Workshop on Rapid System Prototyping 2005: 84-90 - [i2]Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. CoRR abs/cs/0503066 (2005) - [i1]Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. CoRR abs/cs/0510039 (2005) - 2004
- [c4]Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner:
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers 2004: 404-418 - [c3]Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich:
A Dynamic NoC Approach for Communication in Reconfigurable Devices. FPL 2004: 1032-1036 - [c2]Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel:
Flexible Overhead Processing Architectures for G.709 Optical Transport Networks. MBMV 2004: 156-164 - [c1]Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich:
Task scheduling for heterogeneous reconfigurable computers. SBCCI 2004: 22-27
Coauthor Index
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