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ORCIDM. Akif Özkan
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2020 – today
- 2024
[b1]M. Akif Özkan:
Declarative Programming Techniques for Hardware Synthesis of Image Processing Applications. University of Erlangen-Nuremberg, Germany, 2024- 2022
- [j4]Jan Sommer, M. Akif Özkan
, Oliver Keszöcze, Jürgen Teich:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3767-3778 (2022) - [c10]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. FPL 2022: 160-166 - [i4]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. CoRR abs/2203.11028 (2022) - [i3]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. CoRR abs/2203.12437 (2022) - 2021
- [j3]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. 18(3): 765-777 (2021) - 2020
- [j2]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig:
AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3202-3214 (2020) - [c9]Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig:
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC 2020: 1-6 - [c8]Bo Qiao, Oliver Reiche, M. Akif Özkan, Jürgen Teich, Frank Hannig:
Efficient parallel reduction on GPUs with Hipacc. SCOPES 2020: 58-61 - [i2]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig:
AnyHLS: High-Level Synthesis with Partial Evaluation. CoRR abs/2002.05796 (2020) - [i1]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: Wedding of OpenVX and DSL-based Code Generation. CoRR abs/2008.11476 (2020)
2010 – 2019
- 2018
- [j1]Oliver Reiche, M. Akif Ozkan, Frank Hannig, Jürgen Teich, Moritz Schmid:
Loop Parallelization Techniques for FPGA Accelerator Synthesis. J. Signal Process. Syst. 90(1): 3-27 (2018) - [c7]Furkan Aydin, H. Fatih Ugurdag, Vecdi Emre Levent, Aydin Emre Guzel, N. Fajar R. Annafianto, M. Akif Ozkan, Toygar Akgün, Cengiz Erbas:
Rapid Design of Real-Time Image Fusion on FPGA using HLS and Other Techniques. AICCSA 2018: 1-6 - 2017
- [c6]M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich:
Hardware design and analysis of efficient loop coarsening and border handling for image processing. ASAP 2017: 155-163 - [c5]Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig:
Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). ICCAD 2017: 1026-1033 - 2016
- [c4]Aydin Emre Guzel, Vecdi Emre Levent, Mustafa Tosun, M. Akif Ozkan, Toygar Akgün, Duygu Buyukaydin, Cengiz Erbas, H. Fatih Ugurdag:
Using high-level synthesis for rapid design of video processing pipes. EWDTS 2016: 1-4 - [c3]Mustafa Tosun, M. Akif Ozkan, Aydin Emre Guzel, H. Fatih Ugurdag:
Fast one- and two-pick fixed-priority selection and muxing circuits. EWDTS 2016: 1-4 - [c2]M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich:
FPGA-based accelerator design from a domain-specific language. FPL 2016: 1-9 - [c1]Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich:
Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS 2016: 211-218
Coauthor Index
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