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ORCIDSundararajan Sriram
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2000 – 2009
- 2001
[j4]Sundararajan Sriram, Srinath Hosur:
Cyclically permutable codes for rapid acquisition in DS-CDMA systems with asynchronous base stations. IEEE J. Sel. Areas Commun. 19(1): 83-94 (2001)
1990 – 1999
- 1999
- [c6]Sundararajan Sriram, Srinath Hosur:
Fast acquisition method for DS-CDMA systems employing asynchronous base stations. ICC 1999: 1928-1932 - 1998
- [c5]Dale E. Hocevar, Ching-Yu Hung, Dan Pickens, Sundararajan Sriram:
Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example. Great Lakes Symposium on VLSI 1998: 400- - 1997
- [j3]Jürgen Teich, Lothar Thiele, Sundararajan Sriram, Michael Martin:
Performance analysis and optimization of mixed asynchronous synchronous systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 473-484 (1997) - [j2]Shuvra S. Bhattacharyya
, Sundararajan Sriram, Edward A. Lee:
Optimizing synchronization in multiprocessor DSP systems. IEEE Trans. Signal Process. 45(6): 1605-1618 (1997) - [j1]Sundararajan Sriram, Edward A. Lee:
Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors. J. VLSI Signal Process. 15(3): 207-220 (1997) - 1996
- [c4]Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee:
Latency-constrained Resynchronization for Multiprocessor DSP Implementation. ASAP 1996: 365-380 - [c3]Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee:
Self-Timed Resynchronization: A Post-Optimization for Static Multiprocessor Schedules. IPPS 1996: 199-205 - 1995
- [c2]Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee:
Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems. ASAP 1995: 298-309 - 1993
- [c1]Sundararajan Sriram, Edward A. Lee:
Design and implementation of an ordered memory access architecture. ICASSP (1) 1993: 345-348
Coauthor Index
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