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ORCIDIntegration, Volume 14
Volume 14, Number 1, November 1992
- Jingling Xue
, Christian Lengauer:
The synthesis of control signals for one-dimensional systolic arrays. 1-32 - Atsushi Takahashi, Yoji Kajitani:
Peel-the-box: a concept of switch-box routing and tractable problems. 33-47 - Jason Cong, Bryan Preas:
A new algorithm for standard cell global routing. 49-65 - Antonije D. Jovanovic:
Flexible optimal channel routing for critical nets. 67-90 - Karl-Heinz Erhard, Frank M. Johannes:
Power/ground networks in VLSI: are general graphs better than trees? 91-109
Volume 14, Number 2, December 1992
- Susanne E. Hambrusch, Hung-Yi Tu:
Minimizing total wire length during 1-dimensional compaction. 113-144 - Alessandro De Gloria, Paolo Faraboschi:
Massive parallelism in multi-level simulation of VLSI circuits. 145-171 - Afonso G. Ferreira, Siang Wun Song:
Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach. 173-195 - Paul Stravers, Eric Aardoom:
A processor framework customized for navigation computations. 197-214 - Nick Kanopoulos, Joseph H. Carabetta:
Design and implementation of a totally self-checking 16 × 16 bit array multiplier. 215-228
Volume 14, Number 3, February 1993
- Patrice Quinton, Yves Robert:
Introduction to the special issue on algorithms and architectures. i-iii - John G. McWhirter, Ian K. Proudler:
Orthogonal lattice algorithms for adaptive filtering and beamforming. 231-247 - Ravi Varadarajan, Bhavani Ravichandran:
Refinement based techniques for mapping nested loop algorithms onto linear systolic arrays. 249-277 - Sanjay V. Rajopadhye:
An improved systolic algorithm for the algebraic path problem. 279-296 - Jürgen Teich, Lothar Thiele:
Partitioning of processor arrays: a piecewise regular approach. 297-332 - Wayne W. C. Luk:
Systematic serialisation of array-based architectures. 333-360 - Gilles Privat, Alain D. Wittmann:
Pipelined recursive filter architectures for subband image coding. 361-379
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