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ORCIDThe Journal of Signal Processing Systems, Volume 51
Volume 51, Number 1, April 2008
- George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong
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Guest Editorial: Field Programmable Technology. 1-2 - Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos:
Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. 3-21 - Sebastian Lange, Martin Middendorf:
Design Aspects of Multi-level Reconfigurable Architectures. 23-37 - Ralf Laue, Sorin A. Huss:
Parallel Memory Architecture for Elliptic Curve Cryptography over GF(p) Aimed at Efficient FPGA Implementation. 39-55 - Edmund Lee, Guy Lemieux, Shahriar Mirabbasi:
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. 57-76 - Brian M. H. Li, Philip Heng Wai Leong:
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors. 77-98 - Ioannis Sourdis, João Bispo, João M. P. Cardoso, Stamatis Vassiliadis:
Regular Expression Matching in Reconfigurable Hardware. 99-121 - Daniel Ziener, Jürgen Teich:
Power Signature Watermarking of IP Cores for FPGAs. 123-136
Volume 51, Number 2, May 2008
- Najet Boughanmi, Yeqiong Song:
A New Routing Metric for Satisfying Both Energy and Delay Constraints in Wireless Sensor Networks. 137-143 - Limin Sun, Hongsong Zhu, Bin Duan, Xiaowei Li, Yi Sun:
Analysis of Forwarding Mechanisms on Fine-Grain Gradient Sinking Model in WSN. 145-159 - Yu Hen Hu, Xiaohong Sheng:
Dynamic Sensor Self-Organization for Distributive Moving Target Tracking. 161-171 - Wei Liu, Li Cui, Xiaoguang Niu:
EasiTPQ: QoS-Based Topology Control in Wireless Sensor Network. 173-181 - Zheng Wu, Yi Sun, Jiankang Wu, Shiwei Ye:
Robust Multi-Path Zone Routing Protocol for Video Transport Over Reconfigurable Wireless Networks. 183-194 - Jian Ma, Canfeng Chen, Jyri P. Salomaa:
mWSN for Large Scale Mobile Sensing. 195-206
Volume 51, Number 3, June 2008
- Yen-Kuang Chen, David W. Lin, John V. McCanny, Edwin Hsing-Mean Sha:
Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication. 207-208 - Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao:
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. 209-223 - Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont:
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. 225-243 - Shuenn-Shyang Wang, Chien-Sung Li:
An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor. 245-256 - Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee:
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch. 257-268 - Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee:
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores. 269-288 - Wonchul Lee, Hyojin Choi, Wonyong Sung:
Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP. 289-302
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