default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID24th ICECS 2018: Bordeaux, France
- 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018. IEEE 2018, ISBN 978-1-5386-9562-3
- Edoardo Charbon, Claudio Bruschini
, Myung-Jae Lee:
3D-Stacked CMOS SPAD Image Sensors: Technology and Applications. 1-4 - Vincenzo Sesta, Federica A. Villa, Enrico Conca, Alberto Tosi:
A novel sub-10 ps resolution TDC for CMOS SPAD array. 5-8 - Bernhard Goll, Michael Hofbauer, Bernhard Steindl, Horst Zimmermann:
Transient Response of a 0.35µm CMOS SPAD with Thick Absorption Zone. 9-12 - Daniel Morrison, Simon Kennedy, Dennis Delic, Mehmet R. Yuce, Jean-Michel Redoute:
A Triple Integration Timing Scheme for SPAD Time of Flight Imaging Sensors in 130 nm CMOS. 13-16 - Maik Beer, Charles Thattil, Jan F. Haase, Werner Brockherde, Rainer Kokozinski:
2×192 Pixel CMOS SPAD-Based Flash LiDAR Sensor with Adjustable Background Rejection. 17-20 - Antonio Passamani, Davide Ponton, Andreas Wolter, Gerhard Knoblinger, Andrea Bevilacqua:
A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner. 21-24 - Soenke Vehring, Georg Böck:
Compact Transformerless K-Band PA with more than 33% PAE and 14.8 dBm Output Power in 65 nm Bulk CMOS. 25-28 - Giap Luong, Eric Kerherve, Jean-Marie Pham, Pierre Medrel:
Design of 65-nm CMOS Transformer-Based Impedance Matching for LTE Power Amplifier Applications. 29-32 - Jeroen Ponte, Ali Ghahremani, Maikel Huiskamp, Anne-Johan Annema, Bram Nauta:
Augmentation of Class-E PA Reliability under Load Mismatch Conditions. 33-36 - Potereau Manuel, Nathalie Deltimple, Anthony Ghiotto, Dematos Magali:
A 17.3-20.2 GHz Fully Integrated Linear Balanced Power Amplifier in 130nm BiCMOS Technology. 37-40 - Sami Ur Rehman, Ali Ferchichi, Mohammad Mahdi Khafaji, Corrado Carta, Frank Ellinger:
A 1-60 GHz 9.6 mW 0.18 V Output-Swing Static Clock Divider Circuit in 45-nm SOI CMOS. 41-44 - Bortecene Terlemez, Burak Dundar:
A Novel Half-Rate Dual-Response Phase Detector Implementation for a 25-28.3 Gb/s Clock and Data Recovery Circuit. 45-48 - Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion. 49-52 - Simon Buhr, Martin Kreißig, Frank Ellinger:
Low Power 16 Phase Ring Oscillator and PLL for Use in sub-ns Time Synchronization over Ethernet. 53-56 - Shinya Ubukata, Satoshi Komatsu:
A Framework for Automatic Generation of Fully Synthesizable ADPLL. 57-60 - Lina Shi, Wei Li, Xun Zhang, Yue Zhang, Gaojie Chen, Andrei Vladimirescu:
Experimental 5G New Radio integration with VLC. 61-64 - Guillaume Ferré, Audrey Giremus:
LoRa Physical Layer Principle and Performance Analysis. 65-68 - Prasidh Ramabadran, David Malone, Sidath Madhuwantha, Pavel Afanasyev, Ronan Farrell, John Dooley, Bill O'Brien:
A Novel Physical Layer Encryption Scheme to Counter Eavesdroppers in Wireless Communications. 69-72 - Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Hardware design of Euclidean Projection modules for ADMM LDPC decoding. 73-76 - Byeong Yong Kong, Jaehwan Jung, In-Cheol Park:
Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors. 77-80 - Kathirgamaraja Pradeep, Kamalakkannan Kamalavasan, Ratnasegar Natheesan, Ajith Pasqual:
EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGA. 81-84 - Martin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf:
Constant Matrix Multiplication with Ternary Adders. 85-88 - Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
From multicore LDPC decoder implementations to FPGA decoder architectures: a case study. 89-92 - Mohamed F. Tolba, Wafaa S. Sayed, Ahmed G. Radwan, Salwa K. Abd-El-Hafiz, Ahmed M. Soliman:
Permutation-Only FPGA Realization of Real-Time Speech Encryption. 93-96 - Vasileios Kitsakis, Elissaios-Alexios Papatheofanous, Dionisios I. Reisis, George Lentaris, Dimitrios Soudris:
Parity Based In-Place FFT Architecture for Continuous Flow Applications. 97-100 - Eric Gutierrez, Pieter Rombouts, Luis Hernández:
Why and How VCO-based ADCs can improve instrumentation applications. 101-104 - Takamoto Watanabe:
All-Digital-Very-Scalable-ADC TAD Showing Scaling-Effect in 40/16nm-CMOS Technology. 105-108 - Mark Vesterbacka, Vishnu Unnikrishnan:
Ring Counters as Phase Accumulator in VCO-Based ADCs. 109-112 - Mohammadhadi Danesh, Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal:
Ring Oscillator Based Delta-Sigma ADCs. 113-116 - Georges G. E. Gielen, Jorge Marin, Elisa Sacco:
Improving the robustness and drift resilience of CMOS BBPLL-based time-based sensor interfaces. 117-120 - Julio Saldaña Pumarica, Emilio Del-Moral-Hernandez:
A CMOS Squarer Based Nonlinear Filter for Spike Detection. 121-124 - Assefa Kassa Teshome, Behailu Kibret, Daniel T. H. Lai:
An Integrated Sensor IBC Implant Transceiver. 125-128 - Atef H. Bondok, Ahmed Shalaby, Mohammed Sharaf Sayed:
A Low Power Packet Detection Algorithm for FM-UWB PHY for IEEE 802.15.6 WBAN. 133-136 - Juan Manuel Lopez-Martinez, Ion Vornicu, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez:
An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation. 137-140 - Nicola Massari, Hesong Xu:
A new quantum random generator based on a single photon position sensitive device. 141-144 - Mohammed Bedier, Gwenael Bechet, Franck Badets:
Analytical Compact Model for PMUTs Interfaces. 145-148 - Iván Zamora, Eyglis Ledesma, Arantxa Uranga, Núria Barniol:
Fully Integrated CMOS-PMUT Transceiver. 149-152 - Panagiotis Giounanlis, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski:
Occupancy Oscillations and Electron Transfer in Multiple-Quantum-Dot Qubits and their Circuit Representation. 153-156 - Pascal Vivet, Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude:
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. 157-160 - Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning. 161-164 - Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi:
Low-Power Resistive Associative Processor Implementation Through the Multi-Compare. 165-168 - Anna Gregorio, Federico Alimenti:
CubeSats for Future Science and Internet of Space: Challenges and Opportunities. 169-172 - Uroschanit Yodprasit, Marcel Kroh, Stefan Simon, Thomas Mausolf, Wolfgang Winkler:
A Fully-Integrated 60-GHz Voltage-Controlled Oscillator Synchronized by Optoelectronic Signal. 173-176 - Hugo Vallee, Thierry Taris, Thierry Mesnard, Gilles Montoriol, Xavier Hours:
A 1-9 GHz wideband downconverter with noise cancellation and Gm-boosted transconductance cell. 177-180 - Pierre Bisiaux, Francois Rivet, Yoan Veyrac, Yann Deval:
Experimental Demonstration of a 65 nm Integrated CMOS Waveform Generator for 5G sub-6GHz Standard. 181-184 - Mirko Maldari, Karima Amara, Ismael Rattalino, Chadi Jabbour, Patricia Desgreys:
Human Body Communication Channel Characterization for Leadless Cardiac Pacemakers. 185-188 - Mathieu Acchiardi, Jonathan Kern, Guillaume Ferré:
Internet of Wine: A Low-cost Solution for Stock Management Improvement. 189-192 - Alessandro Via Piana Saggiorato, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
HEVC Residual Syntax Elements Generation Architecture for High-Throughput CABAC Design. 193-196 - Luiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel:
On HEVC Robustness to Integer Motion Estimation Pruning. 197-200 - Gustavo Sanchez, Ramon Fernandes, Rodrigo Cataldo, Luciano Agostini, César A. M. Marcon:
Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p Videos. 201-204 - Ramon Fernandes, Gustavo Sanchez, Rodrigo Cataldo, Luciano Agostini, César A. M. Marcon:
Least-Squares Approximation Surfaces for High Quality Intra-Frame Prediction in Future Video Standards. 205-208 - Shuto Kanzaki, Tetsuya Hirose, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa:
Switched-Capacitor Voltage Buck Converter with Step-Down-Ratio and Clock-Frequency Controllers for Ultra-Low-Power IoT Devices. 209-212 - Leo Rolff, Eva Schulte Bocholt, Ralf Wunderlich, Stefan Heinen:
An Integrated Low Drop Out Regulator with Independent Self Biasing Start Up Circuit. 213-216 - Abhishek Koneru, Aida Todri-Sanial, Krishnendu Chakrabarty:
Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-Simulation. 217-220 - Seungchul Jung, Sang Joon Kim:
Single Inductor Multiple Output Buck Converter with Auxiliary Current Source Based Control. 221-224 - Tobias Saalfeld, Markus Scholl, Christoph Beyerstedt, Ralf Wunderlich, Stefan Heinen:
A Tracking Quantizer for Continuous Time Quadrature Bandpass Sigma-Delta Modulators. 225-228 - Abdullah Alshehri, Mohammed Al-Qadasi, Abdullah S. Almansouri, Talal Al-Attar, Hossein Fariborzi:
StrongARM Latch Comparator Performance Enhancement by Implementing Clocked Forward Body Biasing. 229-232 - Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering. 233-236 - Wagner Penny, Mariana Ucker, Italo Machado, Luciano Agostini, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt:
Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator. 237-240 - Francesco Renzini, Davide Rossi, Eleonora Franchi Scarselli, Claudio Mucci, Roberto Canegallo:
A Fully Programmable eFPGA-Augmented SoC for Smart-Power Applications. 241-244 - Mohammad Mohammad, Iraklis Anagnostopoulos:
DROP: Distributed Run-Time and Power Constraint Mapping for Many-Core Systems. 245-248 - Costas Efstathiou, K. Dimolikas, Christoforos Papaioannou, Yiorgos Tsiatouhas:
Low Power and High Speed Static CMOS Digital Magnitude Comparators. 249-252 - Emmanuel A. Gonzalez, Vassilis Alimisis, Costas Psychalinos, Aleksei Tepljakov:
Design of a Generalized Fractional-Order PID Controller Using Operational Amplifiers. 253-256 - Izzet Cem Göknar, Elham Minayi:
A Rectifier Circuit Using Add-Differentiate IC with a Minimal Number of CMOS Transistors. 257-260 - Nathan Seutin, Hugo Garcia-Vazquez, Alexandre Quenon, Fortunato Carlos Dualibe:
Design of a Low-Voltage EEG Detector Based on a Chopping Amplifier in CMOS 65-nm. 261-264 - Jordan Lee Gauci, Edward Gatt, Owen Casha, Giacinto De Cataldo, Ivan Grech, Joseph Micallef:
Design of a Quasi-Linear Rail-to-Rail Delay Element with an Extended Programmable Range. 265-268 - C. Bauza, Josep Maria Sánchez-Chiva, Jordi Madrenas, Daniel Fernández:
Optimizing Power Consumption vs. Linearization in CMFB Amplifiers with Source Degeneration. 269-272 - Hyun Kook Park, Tae Woo Oh, Seong-Ook Jung:
A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation. 273-276 - Hakan Çetinkaya, Ali Zeki, Alper Girgin, Enver Derun Karabeyoglu, Tufan Coskun Karalar:
A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. 277-280 - Abderrahmane Ghimouz, Fatah Rarbi, Laurent Gallin-Martel, Olivier Rossetto:
A Preamplifier-discriminator circuit based on a Common Gate Feedforward TIA for fast time measurements using diamond detectors. 281-284 - Yann Bacher, L. Quazzo, Nicolas Froidevaux, Henri Braquet, Gilles Jacquemod:
Near field measurement bench and on-chip sensor for FTB stress propagation analysis. 285-288 - Marta Franceschi, Alberto Nannarelli, Maurizio Valle:
Tunable Floating-Point for Artificial Neural Networks. 289-292 - Viet-Duc Pham, Hakim Takhedmit, Laurent Cirio:
Performance Improvement of a 2.4-GHz Multi-stage Rectifier Using Power Optimized Waveforms. 293-296 - Seyed Hossein Daneshvar, Mohammad Maymandi-Nejad, Mehmet Rasit Yuce, Jean-Michel Redoute:
Power Efficient Optimization Procedure for Asynchronous Electrostatic Generators. 297-300 - Sonia Abdellatif, Brahim Mezghani, Fares Tounsi, Frédérick Mailly, Pascal Nouet:
Mechanical Solution for Out-of-Plane Sensitivity Enhancement of CMOS MEMS Convective Accelerometers. 301-304 - Abdul Hafiz Alameh, Mathieu Gratuze, Alexandre Robichaud, Frederic Nabki:
Study and Design of MEMS Cross-Shaped Piezoelectric Vibration Energy Harvesters. 305-308 - Fayçal Saada, Andreas Zeiner, Kévin Meder, Laura Garcia-Gamez, Loïc Bernard:
Miniaturized onboard electronics for attitude measurement of medium caliber projectiles. 309-312 - Christoph Beyerstedt, Vahid Bonehi, Tobias Saalfeld, Markus Scholl, Ralf Wunderlich, Stefan Heinen:
Analysis and Design of a Passive Sliding IF Mixer With a Novel Built-in Gainstep Mechanism for an Integrated 2.4 GHz RF-Receiver. 313-316 - Xin An, Jens Wagner, Frank Ellinger:
A 7th Derivative Gaussian Pulse Generator for IR-UWB Radar Applications in Pedestrian Detection. 317-320 - Teng Cheng, Sut-Kam Ho, Kam-Weng Tam, Wai-Wa Choi, Guang-Hua Yang:
A Novel Cross-shaped Bandpass Filter with Reconfigurable Notch Band. 321-324 - Amani Aloui, Ons Ben Rhouma, Chiheb Rebai:
Preamble based SNR estimation for IEEE 802.15.4g MR-OFDM. 325-328 - T. First, André Augusto Mariano, Polyana Camargo de Lacerda, Glauber Brante, O. C. Gouveia Filho, Bernardo Leite:
2.4 GHz Reconfigurable Low Voltage and Low Power VCO dedicated to Sensor Networks Applications. 329-332 - Jigme Zangpo, Ricardo Povoa, Jorge Guilherme, Nuno Horta:
An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations. 333-336 - Anaël Lohou, David Chaimbault, Benoît Lesur, Alain Karas, Julien Lintignat, Bernard Jarry:
Ka-band MMIC Variable Gain Low Noise Amplifier for Electronic Scanning Antenna. 337-340 - Zahra Katbay, Rabie Jabasini, Mohammed Ismail, Ali Sibaie:
Miniature Dual Band Antenna for WPT application. 341-344 - Achraf Waguaf, Romain Alvernhe, Ludivine Fadel, Marjorie Grzeskowiak:
Energy Harvesting with 2.45 GHz Rectenna for urban application. 345-348 - Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino:
A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection. 349-352 - Gilles Montoriol, Piotr Kawka, Vincent Poisson:
Car Radar Transceiver 80GHz Design Improvements Using EM-Cosimulation Flow. 353-356 - Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa Jr., Paulo F. Butzen:
Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults. 357-360 - Marko S. Andjelkovic, Milan Babic, Yuanqing Li, Oliver Schrape, Milos Krstic, Rolf Kraemer:
Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates. 361-364 - Gustavo L. Lima, Nelson de Farias Traversi, Diana Francisca Adamatti, Graçaliz Pereira Dimuro, Cristina Meinhardt, Eduardo Wenzel Brião, Odorico Machado Mendizabal:
Exploring MAS to a High Level Abstration NoC Simulation Environment. 365-368 - Winston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli:
Integrated ESOP Refactoring for Industrial Designs. 369-372 - Mohammed Al-Qadasi, Abdullah Alshehri, Talal Al-Attar, Hossein Fariborzi:
A Self-Biased Schmitt Trigger for Low Power Applications. 373-376 - Lukás Sekanina, Vojtech Mrazek, Zdenek Vasícek:
Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. 377-380 - Victor Arribas, Svetla Nikova, Vincent Rijmen:
VerMI: Verification Tool for Masked Implementations. 381-384 - Tim Güneysu, Markus Krausz, Tobias Oder, Julian Speith:
Evaluation of Lattice-Based Signature Schemes in Embedded Systems. 385-388 - Filippos Pirpilidis, Lampros Pyrgas, Paris Kitsos:
A 4-bit Architecture of SEED Block Cipher for IoT Applications. 389-392 - Maxime Montoya, Thomas Hiscock, Simone Bacles-Min, Anca Molnos, Jacques J. A. Fournier:
Energy-efficient Masking of the Trivium Stream Cipher. 393-396 - Kais Chibani, Adrien Facon, Sylvain Guilley, Youssef Souissi:
Technology-agnostic power optimization for AES block cipher. 397-400 - Kateryna Stoyka, Giulia Di Capua, Nicola Femia:
Modeling of Stepped Air-Gap Ferrite Inductors in Switching Power Supplies. 401-404 - Andrii Sokolov, Dhiman Mallick, Saibal Roy, Michael Peter Kennedy, Elena Blokhina:
Novel Approach to Modelling Electromechanical Coupling and Testing its Self-Consistency in Micro-Scale Kinetic Electromagnetic Energy Harvesters. 405-408 - Igor M. Filanovsky:
On 60 GHz Solid-State Transformers Designed in 65 nm CMOS Technology. 409-412 - David Alejandro Fernandez Guzman, Enrico Macrelli, Danilo Demarchi, Marco Crepaldi:
High-Accuracy Wireless 6DOF Magnetic Tracking System Based on FEM Modeling. 413-416 - Nicola Femia, Giulia Di Capua:
Hysteretic Regulators with Partially-Saturated Inductors. 417-420 - Nassima Kadri, Ala-Eddine Yahiaoui, Mohamed Mehdi Kandi, Mouloud Koudil:
FTNoCSim: A new Simulation platform for Evaluating Network-on-Chip Reliability. 421-424 - Douglas Lohmann, Alexis Huf, Djones Lettnin, Frank Siqueira, José Luís Güntzel:
A Domain-specific Language for Automated Fault Injection in SystemC Models. 425-428 - Vitor G. Lima, Plinio Finkenauer, Vinicius V. Camargo, Felipe S. Marques, Leomar R. Junior, Rafael Iankowski Soares:
A Novel Sizing Method Aiming Security Against Differential Power Analysis. 429-432 - Matheus F. Pontes, Paulo F. Butzen, Rafael B. Schvittz, Leomar S. da Rosa Jr., Denis Teixeira Franco:
The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits. 433-436 - Marwan Ammar, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria:
Reliability Analysis of the SPARC V8 Architecture via Fault Trees and UPPAL-SMC. 437-440 - Matthew Love, Mury Thian, Floris van der Wilt, Koen van Hartingsveldt, Kave Kianush:
A Compact 5 GHz Lumped-Element Wilkinson Power Combiner on 28 nm Bulk CMOS. 441-444 - Jan Cools, Thibaut Gurne, Patrick Reynaert:
A Broadband 13 Vpp 40% PAE Stacked Line Driver in 28 nm Bulk CMOS. 445-448 - Saadou Al Mokdad, Raafat Lababidi, Marc Le Roy, Sawsan Sadek, André Pérennec, Denis Le Jeune:
Wide-band Active Tunable Phase Shifter Using Improved Non-Foster circuit. 449-452 - Andrey A. Kokolov, Leonid I. Babak, Dmitriy A. Zhabin, Feodor I. Sheyerman, Alexey V. Drozdov:
Automated Synthesis of 1.5-5 GHz SiGe BiCMOS Differential Amplifiers Loaded on Resistive and Complex-Impedance Terminations. 453-456 - Jiawen Hu, Liu Chen, Yifei Hu:
A Current Balanced Multi-Phase Class-D Amplifier for Wideband Supply Modulator. 457-460 - Ekta Sharma, Emmanuel Pistono, Philippe Ferrari, Sylvain Bourdel:
80 GHz VCO with Slow-wave Coplanar Stripline Synthesized Differential Inductor. 461-464 - Leidy Mabel Alvero-Gonzalez, Eric Gutierrez, Luis Hernández:
A Highly Linear Ring Oscillator for VCO-based ADCs in 65-nm CMOS. 465-468 - Ningcheng Gaoding, Jean-Francois Bousquet:
A Fully Integrated Sub-GHz Inductor-less VCO with a Frequency Doubler. 469-472 - Fayrouz Haddad, Imen Ghorbel, Wenceslas Rahajandraibe, Mourad Loulou, Abdelhalim Slimane:
Current-reuse RF LC-VCO Design for Autonomous Connected Objects. 473-476 - Dimitrios Tychalas, Michail Maniatakos:
Open Platform Systems Under Scrutiny: A Cybersecurity Analysis of the Device Tree. 477-480 - Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Johanna Sepúlveda:
Enabling Secure MPSoC Dynamic Operation through Protected Communication. 481-484 - Maria Mushtaq, Ayaz Akram, Muhammad Khurram Bhatti, Maham Chaudhry, Muhammad Muneeb Yousaf, Umer Farooq, Vianney Lapotre, Guy Gogniat:
Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-time. 485-488 - El Mehdi Benhani, Lilian Bossuet:
DVFS as a Security Failure of TrustZone-enabled Heterogeneous SoC. 489-492 - Franck Courbon:
Challenges and examples of in-situ memory content extraction techniques. 493-496 - Alfio Dario Grasso, Salvatore Pennisi:
Ultra-Low Power Amplifiers for IoT Nodes. 497-500 - Siamak Delshadpour:
A Low Power CMOS gm-C Polyphase Filter for Low-IF GPS Receiver. 501-504 - Gianluca Giustolisi, Gaetano Palumbo:
Design of CMOS OTAs with Settling-Time Constraints. 505-508 - Yannick Wenger, Bernd Meinerzhagen, A. Ghazinour:
Current-mode Temperature Compensation for a Differential Logarithmic Amplifier in 180nm BiCMOS. 509-512 - Mattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
Slicing FIFOs for on-chip memory bandwidth exhaustion. 513-516 - Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura:
Isolation-Safe Speculative Access Control for Hardware Transactional Memory. 517-520 - Iago Storch, Bruno Zatt, Luciano Volcan Agostini, Guilherme Corrêa, Daniel Palomino:
Memory-Aware Tiles Workload Balance through Machine-Learnt Complexity Reduction for HEVC. 521-524 - Ioannis Kouretas, Vassilis Paliouras:
Hardware aspects of Long Short Term Memory. 525-528 - Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura:
An Analysis and a Solution of False Conflicts for Hardware Transactional Memory. 529-532 - Zbigniew Galias:
Computation of Topological Entropy of Finite Representations of Maps. 533-536 - Fereidoon Hashemi Noshahr, Mohamad Sawan:
Analog-based Compressive Sensing of Multichannel Neural Signals: Systematic Design Approaches. 537-540 - Alon Ascoli, Ioannis Messaris, Ronald Tetzlaff, Leon O. Chua:
CNNs with bistable-like non-volatile memristors: a novel mem-computing paradigm for the IoT era. 541-544 - Bartlomiej Garda, Zbigniew Galias:
Modeling of Memristors Under Sinusoidal Excitations with Various Frequencies. 545-548 - Anastasios Petropoulos, Theodore Antonakopoulos:
Accurate PCM Crosspoint Emulator and its Use on Eigenvalues Calculation. 549-552 - Nicolas Locatelli, Adrien F. Vincent, Damien Querlioz:
Use of Magnetoresistive Random-Access Memory as Approximate Memory for Training Neural Networks. 553-556 - Charly Meyer, Andre Chanthbouala, Soren Boyn, Jean Tomas, Vincent Garcia, Manuel Bibes, Stephane Fusil, Julie Grollier, Sylvain Saïghi:
Verilog-A model of ferroelectric memristors dedicated to neuromorphic design. 557-560 - Elisa Vianello, Denys R. B. Ly, Selina La Barbera, Thomas Dalgaty, Niccolo Castellani, Gabriele Navarro, Guillaume Bourgeois, Alexandre Valentian, Etienne Nowak, Damien Querlioz:
Metal Oxide Resistive Memory (OxRAM) and Phase Change Memory (PCM) as Artificial Synapses in Spiking Neural Networks. 561-564 - Oscar Camps, Mohamad Moner Al Chawa, Carol de Benito, Miquel Roca, Stavros G. Stavrinides, Rodrigo Picos, Leon O. Chua:
A Purely Digital Memristor Emulator based on a Flux-Charge Model. 565-568 - Pablo Negri, Miguel Soto, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona:
Scene Context Classification with Event-Driven Spiking Deep Neural Networks. 569-572 - Fabio G. Rossato G. da Silva, Cristina Meinhardt, Ricardo Reis:
Impact of Near-Threshold and Variability on 7nm FinFET XOR Circuits. 573-576 - Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri:
10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs. 577-580 - Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells. 581-584 - Amir Shalom, Robert Giterman, Adam Teman:
High Density GC-eDRAM Design in 16nm FinFET. 585-588 - Roman Golman, Robert Giterman, Adam Teman:
Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. 589-592 - Dimitri Galayko, Armine Karami, Philippe Basset, Elena Blokhina:
Kinetic Energy Harvesting for the IoT: Perspectives and Challenges for the Next Decade. 593-596 - Kaung Oo Htet, Jinwei Zhao, Rami Ghannam, Hadi Heidari:
Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant Devices. 597-600 - Pei-Chun Liao, Yi-Lun Chen, Po-Hung Chen:
A Single-Inductor Dual-Ouput (SIDO) DC-DC Converter for Implantable Medical Devices in 180nm Standard CMOS Process. 601-604 - Andrea Ballo, Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo:
A Clock Boosted Charge Pump with Reduced Rise Time. 605-608 - Hussein Assaf, Yvon Savaria, Mohamad Sawan:
Vector Matrix Multiplication Using Crossbar Arrays: A Comparative Analysis. 609-612 - João Alberto de França Ferreira, Emilie Avignon-Meseldzija, Pietro Maris Ferreira, Philippe Bénabès:
Design and Synthesis of Arbitrary Group Delay Filters for Integrated Analog Signal Processing. 613-616 - Kenneth Martin:
Complex Ladder Filter Realizations. 617-620 - Zois-Gerasimos Tasoulas, Iraklis Anagnostopoulos:
Optimizing Performance of GPU Applications with SM Activity Divergence Minimization. 621-624 - Florin Burcea, Andreas Herrmann, Bing Li, Helmut Graeb:
MEMS-IC Optimization Considering Design Parameters and Manufacturing Variation from both Mechanical and Electrical Side. 625-628 - Shahrzad Mahboubi, Hiroshi Ninomiya:
A Novel quasi-Newton with Momentum Training for Microwave Circuit Models using Neural Networks. 629-632 - Jahnavi Kasturi Rangan, Nasim Pour Aryan, Lantao Wang, Jens Bargfrede, Christian Funke, Helmut Graeb:
Design-dependent Monitors Based on Delay Sensitivity Tracking. 633-636 - Duc Vinh Nguyen, L. Werling, Chrystelle Po, Norbert Dumas, Morgan Madec, Wilfried Uhring, Luc Hébrard, Latifa Fakri-Bouchet, Joris Pascal, Y. Wadghiri:
Modeling the effect of strong magnetic field on n-type MOSFET in strong inversion. 637-640 - Ekaterina Kalinicheva, Jérémie Sublime, Maria Trocan:
Neural Network Autoencoder for Change Detection in Satellite Image Time Series. 641-642 - Remy Vauche, H. Bounaceur, S. Zerenini, Nicolas Dehaese, Jean Gaubert, Hervé Barthélemy, Valentin Gies:
Implementation of the Standardized Human Body Communications - A Feasibility Study. 643-644 - Yajian Gan, Remy Vauche, Jean-François Pons, Wenceslas Rahajandraibe:
Dry Electrode Materials for Electrocardiographic Monitoring. 645-646 - Tomoaki Morita, Yohtaro Umeda:
Comparison between Quadrature-modulation EPWM transmitters with a 90° and 180° hybrid in physical models. 647-648 - Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
Study of Stochastic Invertible Multiplier Designs. 649-650 - Haruya Fujii, Lei Lin, Masahiro Fukui:
Experiments of Electric Vehicle Cart Modeling, Calibration, and Optimization. 651-652 - Yuto Tanaka, Yohtaro Umeda, Kyoya Takano:
Power-amplifier-inserted Transversal Filter that Recovers Quantization Noise Power by CMOS Rectifier. 653-654 - Honggui Li, Maria Trocan:
Deep Residual Learning-based Reconstruction of Stacked Autoencoder Representation. 655-656 - Nicolai Behmann, Holger Blume:
Real-Time LED Flicker Detection and Mitigation: Architecture and FPGA-Implementation. 657-658 - Ali Akbari, Marco Trevisi, Maria Trocan:
Adaptive Compressed Sensing Image Reconstruction Using Binary Measurement Matrices. 659-660 - Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis. 661-664 - Nikolaos Dimou, Manolis I. A. Lourakis, George Lentaris, Dimitrios Soudris, Dionysios I. Reisis:
Parallel Robust Absolute Orientation on FPGA for Vision and Robotics. 665-668 - Sho Iwazaki, Koichi Ichige:
Underdetermined Direction of Arrival Estimation by Sum and Difference Composite Co-Array. 669-672 - Yuki Miyauchi, Haruki Mori, Tetsuya Youkawa, Kazuki Yamada, Shintato Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue:
Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth. 673-676 - Simon Lecoq, Jean Le Bellego, Angel Gonzalez, Benoit Larras, Antoine Frappé:
Low-complexity feature extraction unit for "Wake-on-Feature" speech processing. 677-680 - Tuukka Panula, Tero Hurnanen, Jarno Tuominen, Matti Kaisti, Juho Koskinen, Mikko Pänkäälä, Tero Koivisto:
A Wearable Sensor Node for Detecting Atrial Fibrillation Using Real-Time Digital Signal Processing. 681-684 - Robert Becker, Alfred Buck, Volker Commichau, Diogo Di Calafiori, Günther Dissertori, Lubomir Djambazov, Afroditi Eleftheriou, Peter Fischer, Mikiko Ito, Parisa Khateri, Werner Lüstermann, Josep F. Oliver, Christian Ritzer, Michael Ritzert, Ulf Röser, Markus Rudin, Ilaria Sacco, Paola Solevi, Charalampos Tsoumpas, Geoffrey Warnock, Bruno Weber, Matthias T. Wyss, Agnieszka Zagozdzinska-Bochenck:
Dual Ring Prototype Electronic System for the Small Animal Fast Insert for MRI. 685-688 - Beomsang Yoo, Ki-Ryong Kim, Seong-Ook Jung:
Triplet-based Spike Timing Dependent Plasticity Circuit Design for three-terminal Spintronic Synapse. 689-692 - Safouane Noubir, Yannick Bornat, Bertrand Le Gal:
A scalable and efficient digital signal processing system for real time biological spike detection. 697-700 - Sara S. Ghoreishizadeh, Despina Moschou, Dearbhla McBay, Carla Gonalez-Solino, Gorachand Dutta, Mirella Di Lorenzo, Ahmed Soltan:
Towards self-powered and autonomous wearable glucose sensor. 701-704 - Pierre S. Laquintinie, Abhishek Sachan, Jean-François Feller, Cyril Lahuec, Mickael Castro, Fabrice Seguin, Laurent Dupont:
A functionalized carbon nanotube based electronic nose for the detection of nerve agents. 705-708 - Lorenzo Mezzera, Marco Carminati, Michele Di Mauro, Andrea Turolla, Marco Tizzoni, Manuela Antonelli:
A 7-Parameter Platform for Smart and Wireless Networks Monitoring On-Line Water Quality. 709-712 - Naglaa El Agroudy, Mohammed El-Shennawy, Niko Joram, Sami Ur Rehman, Frank Ellinger:
A Precise and Accurate Indoor Localization System based on Sub-Harmonic FMCW Radar. 713-716 - Nico Angeli, Klaus Hofmann:
A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay Lines. 717-720 - Guangda Shi, Renhui Yan, Jianxiong Xi, Lenian He, Wanxin Ding, Wenjie Pan, Zhenqing Liu, Feng Yang, Dongpo Chen:
A Compact 6 ns Propagation Delay 200 Mbps 100 kV/µs CMR Capacitively Coupled Direction Configurable 4-Channel Digital Isolator in Standard CMOS. 721-724 - Ian Assom, Gerardo Molina Salgado, Daniel O'Hare, Ivan John O'Connell, Keith A. O'Donoghue:
A 4th-Order Continuous-Time $\Delta\Sigma$ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC. 725-728 - Baptiste Laporte-Fauret, Guillaume Ferré, Dominique Dallet, Bryce Minger, Loic Fuche:
ADC Resolution for Simultaneous Reception of Two Signals with High Dynamic Range. 729-732 - Gregory Darcheville, Cyril Voillequin, Jean-Baptiste Bégueret:
Direct Digital Frequency Synthesis design methodology for optimized spurs / jitter performances. 733-736 - Irene Degl'Innocenti, Luca Fanucci, Joel Albertone, Andrea Boccardi, Thierry Bogey, Carla Moran Guizan, Manoel Barros Marin, Athanasios Topaloudis, Manfred Wendt:
Digital Acquisition Chain for the Upgrade of the CERN SPS Beam Position Monitor. 737-740 - Maisam Jalilian, Arash Ahmadi, Majid Ahmadi:
Hardware Implementation of A Chaotic Pseudo Random Number Generator Based on 3D Chaotic System without Equilibrium. 741-744 - Kasem Khalil, Omar Eldash, Ashok Kumar, Magdy A. Bayoumi:
An Efficient Approach for Neural Network Architecture. 745-748 - Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello:
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems. 749-752 - Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello:
Designing Fast Convolutional Engines for Deep Learning Applications. 753-756 - Grégory C. Marchesan, Nelson R. Weirich, Eduardo C. Culau, Iacana Ianiski Weber, Fernando Gehm Moraes, Everton Carara, Leonardo Londero de Oliveira:
Exploring RSA Performance up to 4096-bit for Fast Security Processing on a Flexible Instruction Set Architecture Processor. 757-760 - Luciano L. Caimi, Vinicius Fochi, Fernando Gehm Moraes:
Secure Admission of Applications in Many-cores. 761-764 - Timothe Turko, Wilfried Uhring, Foudil Dadouche, Laurent Fesquet:
An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems. 765-768 - Emmanouil Kavvousanos, Vassilis Paliouras, Ioannis Kouretas:
Simplified Deep-Learning-based decoders for linear block codes. 769-772 - Jean Carlo Hamerski, Anderson R. P. Domingues, Fernando Gehm Moraes, Alexandre M. Amory:
Evaluating Serialization for a Publish-Subscribe Based Middleware for MPSoCs. 773-776 - Xiaoting Sun, Yi Guo, Zhenhao Liu, Shinji Kimura:
A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal Processing. 777-780 - Paul Gavrikov, Pascal E. Verboket, Tolgay Ungan, Markus Muller, Matthias Lai, Christian Schindelhauer, Leonhard M. Reindl, Thomas M. Wendt:
Using Bluetooth Low Energy to trigger an ultra-low power FSK wake-up receiver. 781-784 - Mark S. Widmaier, Florin Doru Hutu, Guillaume Villemaud:
Efficiency of Orthogonal Codes for Quasi-passive Wake-Up Radio Receivers using Frequency Footprint IDs. 785-788 - Mickael Maman, Dominique Morche, Baudouin Martineau, Clement Jany, Ivan Miro Panades, Anthony Quelen, Franck Badets, Edith Beigné:
Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols. 789-792 - Alessia Maria Elgani, Michele Magno, Francesco Renzini, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Canegallo, Giulio Ricotti, Luca Benini:
Nanowatt Wake-Up Radios: Discrete-Components and Integrated Architectures. 793-796 - Nour El Hoda Djidi, Antoine Courtay, Matthieu Gautier, Olivier Berder:
Adaptive relaying for wireless sensor networks leveraging wake-up receiver. 797-800 - Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda:
Redundant SAR ADCs with Split-capacitor DAC. 801-804 - Eric Gutierrez, Luis Hernández, Susana Patón, Pieter Rombouts:
Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping. 805-808 - Rubén Garvi, Enrique Prefasi:
A Novel Multi-Bit Sigma-Delta Modulator using an Integrating SAR Noise-Shaped Quantizer. 809-812 - Dong-Jick Min, Sun Youl Choi, Jae Hoon Shim:
A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing Detector. 817-820 - Mustafijur Rahman, Ramesh Harjani:
A 2.4GHz IEEE 802.15.6 Compliant 1.52nJ/bit TX & 1.32nJ/bit RX Multiband Transceiver for Low Power Standards. 821-824 - Michele Spasaro, Domenico Zito:
Input Integrated Matching in RF LNA with Inductive Degeneration in Low-Power Regime. 825-828 - Rui Ma, Martin Kreißig, Frank Ellinger:
A Fast Switchable and Band-Tunable 5-7.5 GHz LNA in 45 nm CMOS SOI Technology for Multi-Standard Wake-up Radios. 829-832 - Andreas Ely, Michele Spasaro, Domenico Zito:
A Study on Extending $f_{\mathrm{T}}$ in TIIMCA LNA Topology. 833-836 - Hendrik P. Nel, Tinus Stander, Fortunato C. Dualibe:
Built-In Oscillation-Based Self-Testing of a 2.4 GHz LNA in 0.35µm CMOS. 837-840 - Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Can Approximate Computing Reduce Power Consumption on FPGAs? 841-844 - Ali Ibrahim, Mario Osta, Mohamad Alameh, Moustafa Saleh, Hussein Chible, Maurizio Valle:
Approximate Computing Methods for Embedded Machine Learning. 845-848 - Darjn Esposito, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli:
Quality-Scalable Approximate LMS Filter. 849-852 - Marco Vacca, Yaswanth Tavva, Anupam Chattopadhyay, Andrea Calimera:
Logic-In-Memory Architecture For Min/Max Search. 853-856 - Marco Carminati, Roland Thewes, Jacob K. Rosenstein, Hoi-Jun Yoo:
Advances and Open Challenges for Integrated Circuits Detecting Bio-Molecules. 857-860 - Olaitan Olabode, Antti Ontronen, Vishnu Unnikrishnan, Marko Kosunen, Jussi Ryynänen:
A VCO-based ADC with Relaxation Oscillator for Biomedical Applications. 861-864 - Henning Schütz, Denis Djekic, Stefan Gambach, Hans Kaim, Raphael Steinhoff, Albrecht Rothermel:
Current Mode Communication Scheme for Subretinal Implants with 8mV RMS Wire Potential. 865-868 - Wei Onn Ting, Sara S. Ghoreishizadeh:
Autonomous readout ASIC with 169dB input dynamic range for amperometric measurement. 869-872 - Gisela De La Fuente-Cortes, A. Díaz-Méndez, Victor R. Gonzalez-Diaz:
A Fully Integrated Fuzzy Logic Algorithm for Ischemic Heartbeat Classification. 873-876
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-19 22:18 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
