"A 1-60 GHz 9.6 mW 0.18 V Output-Swing Static Clock Divider Circuit in ..."

Sami Ur Rehman et al. (2018)

> Home

Details and statistics

DOI: 10.1109/ICECS.2018.8618002

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icecsys/RehmanFKCE18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icecsys/RehmanFKCE18
Sami Ur Rehman, Ali Ferchichi, Mohammad Mahdi Khafaji, Corrado Carta, Frank Ellinger:
A 1-60 GHz 9.6 mW 0.18 V Output-Swing Static Clock Divider Circuit in 45-nm SOI CMOS. ICECS 2018: 41-44

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.