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2020 – today
- 2022
[c14]Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon:
Improving LUT-based optimization for ASICs. DAC 2022: 421-426- [c13]Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee
, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli:
Majority-based Design Flow for AQFP Superconducting Family. DATE 2022: 34-39 - 2021
- [c12]Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
LUT-Based Optimization For ASIC Design Flow. DAC 2021: 871-876 - 2020
- [j3]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access 8: 226828-226844 (2020) - [c11]Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
SAT-Sweeping Enhanced for Logic Synthesis. DAC 2020: 1-6
2010 – 2019
- 2019
- [c10]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Scalable Boolean Methods in a Modern Synthesis Flow. DATE 2019: 1643-1648 - 2018
- [c9]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Improvements to boolean resynthesis. DATE 2018: 755-760 - [c8]Winston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli:
Integrated ESOP Refactoring for Industrial Designs. ICECS 2018: 369-372 - 2017
- [c7]Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Multi-level logic benchmarks: An exactness study. ASP-DAC 2017: 157-162 - [c6]Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Janet Olson:
Logic optimization and synthesis: Trends and directions in industry. DATE 2017: 1303-1305 - [c5]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Enabling exact delay synthesis. ICCAD 2017: 352-359
1990 – 1999
- 1998
- [j2]Luca Benini, Patrick Vuillod, Giovanni De Micheli:
Iterative remapping for logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 948-964 (1998) - 1997
- [j1]Luca Benini, Patrick Vuillod, Alessandro Bogliolo, Giovanni De Micheli:
Clock Skew Optimization for Peak Current Reduction. J. VLSI Signal Process. 16(2-3): 117-130 (1997) - [c4]Patrick Vuillod, Luca Benini, Giovanni De Micheli:
Generalized matching from theory to application. ICCAD 1997: 13-20 - [c3]Patrick Vuillod, Luca Benini, Giovanni De Micheli:
Re-mapping for low power under tight timing constraints. ISLPED 1997: 287-292 - 1996
- [c2]Patrick Vuillod, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli:
Clock skew optimization for peak current reduction. ISLPED 1996: 265-270 - [c1]Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli:
Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. ISSS 1996: 57-
Coauthor Index
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