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ORCIDFelipe S. Marranghello
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2020 – today
- 2022
[j6]Cesar de S. Dias
, Felipe S. Marranghello, Raphael Martins Brum, Paulo F. Butzen:
A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 878-887 (2022)- 2021
- [c20]Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
LUT-Based Optimization For ASIC Design Flow. DAC 2021: 871-876 - 2020
- [j5]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas:
Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test 37(3): 51-58 (2020) - [j4]Augusto Neutzling, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas:
maj-n Logic Synthesis for Emerging Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 747-751 (2020) - [c19]Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
SAT-Sweeping Enhanced for Logic Synthesis. DAC 2020: 1-6
2010 – 2019
- 2019
- [j3]Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Four-Level Forms for Memristive Material Implication Logic. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1228-1232 (2019) - [c18]Felipe S. Marranghello, Yang Yu, Elena Dubrova:
Threshold Physical Unclonable Functions. ISMVL 2019: 55-60 - 2018
- [c17]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas:
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. SBCCI 2018: 1-6 - [c16]Yang Yu, Felipe S. Marranghello, Victor Diges Teijeira, Elena Dubrova:
One-Sided Countermeasures for Side-Channel Attacks Can Backfire. WISEC 2018: 299-301 - 2017
- [j2]Vinícius Dal Bem, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. IEEE Trans. Emerg. Top. Comput. 5(2): 247-259 (2017) - [c15]Jeferson José Baqueta, Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas:
Binary adder circuit design using emerging MIGFET devices. ISQED 2017: 125-130 - 2016
- [c14]Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Performance evaluation of optimized transistor networks built using independent-gate FinFET. LASCAS 2016: 227-230 - 2015
- [j1]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 267-278 (2015) - [c13]Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis:
Enhanced Spin-Diode Synthesis Using Logic Sharing. DSD 2015: 218-224 - [c12]Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
SOP based logic synthesis for memristive IMPLY stateful logic. ICCD 2015: 228-235 - [c11]Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD 2015: 680-687 - [c10]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Fast buffer delay estimation considering time-dependent dielectric breakdown. ISCAS 2015: 177-180 - [c9]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS 2015: 181-184 - 2014
- [c8]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
CMOS inverter analytical delay model considering all operating regions. ISCAS 2014: 1452-1455 - 2013
- [c7]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
CMOS inverter delay model based on DC transfer curve for slow input. ISQED 2013: 651-657 - [c6]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Delay model for static CMOS complex gates. SBCCI 2013: 1-6 - [c5]Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis:
Spin diode network synthesis using functional composition. SBCCI 2013: 1-6 - 2012
- [c4]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Design-oriented delay model for CMOS inverter. SBCCI 2012: 1-6 - 2011
- [c3]Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas, Francesc Moll:
Transistor Sizing Analysis of Regular Fabrics. ARCS Workshops 2011 - [c2]Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD 2011: 279-284 - [c1]Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Francesc Moll, Renato P. Ribas:
Transistor sizing in lithography-aware regular fabrics. SBCCI 2011: 97-102
Coauthor Index
aka: Renato Perez Ribas
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