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Journal Articles
- 2020
[j4]Walter Lau Neto
, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas:
Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test 37(3): 51-58 (2020)- [j3]Augusto Neutzling, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas:
maj-n Logic Synthesis for Emerging Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 747-751 (2020) - 2019
- [j2]Jody Maick Matos, Jordi Carrabina, André Inácio Reis:
Efficiently Mapping VLSI Circuits With Simple Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 692-704 (2019) - [j1]Augusto Neutzling, Jody Maick Matos, Alan Mishchenko, André Inácio Reis, Renato P. Ribas:
Effective Logic Synthesis for Threshold Logic Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 926-937 (2019)
Conference and Workshop Papers
- 2018
- [c7]Jody Maick Matos, André Inácio Reis, Jordi Carrabina:
Technology Mapping for Circuits with Simple Cells. ISCAS 2018: 1-5 - [c6]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas:
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. SBCCI 2018: 1-6 - 2015
- [c5]Augusto Neutzling, Jody Maick Matos, André Inácio Reis, Renato P. Ribas, Alan Mishchenko:
Threshold Logic Synthesis Based on Cut Pruning. ICCAD 2015: 494-499 - [c4]Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen:
Open Cell Library in 15nm FreePDK Technology. ISPD 2015: 171-178 - [c3]Jody Maick Matos, Augusto Neutzling, Renato P. Ribas, André Inácio Reis:
A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design. ISPD 2015: 185-192 - 2014
- [c2]Manuel Llamas, Mohammad Mashayekhi, Jordi Carrabina, Jody Maick Matos, André Inácio Reis:
Optimization on cell-library design for digital Application Specific Printed Electronics Circuits. PATMOS 2014: 1-6 - [c1]Jody Maick Matos, Marcus Ritt, Renato P. Ribas, André Inácio Reis:
Deriving Reduced Transistor Count Circuits from AIGs. SBCCI 2014: 40:1-40:7
Parts in Books or Collections
- 2018
- [p1]André Inácio Reis, Jody M. A. Matos:
Physical Awareness Starting at Technology-Independent Logic Synthesis. Advanced Logic Synthesis 2018: 69-101
Coauthor Index
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