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ORCIDJorge Guilherme
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2020 – today
- 2022
[c30]Fábio Passos, Rafael Vieira, António Canelas, Ricardo Póvoa, Nuno Lourenço, Nuno Horta
, Jorge Guilherme:
A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications. ISCAS 2022: 1-5- [c29]Nuno Lourenço, Fábio Passos, Rafael Vieira, Ricardo Martins, Nuno Horta, Jorge Guilherme, Ricardo Póvoa:
Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient. SMACD 2022: 1-4 - [c28]Rafael Vieira, Fábio Passos, Ricardo Povoa, Ricardo Martins, Nuno Horta, Jorge Guilherme, Nuno Lourenço:
Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling. SMACD 2022: 1-4 - 2020
- [j8]António Canelas, Ricardo Póvoa, Ricardo Martins, Nuno Lourenço, Jorge Guilherme, João Paulo Carvalho, Nuno Horta:
FUZYE: A Fuzzy c-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 1-13 (2020)
2010 – 2019
- 2018
- [j7]Jonathan Calvillo, Ricardo Póvoa, Jorge Guilherme, Nuno Horta:
Second-order compensation BGR with low TC and high performance for space applications. Integr. 63: 256-265 (2018) - [c27]Jigme Zangpo, Ricardo Povoa, Jorge Guilherme, Nuno Horta:
An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations. ICECS 2018: 333-336 - [c26]Rodrigo Granja, Mauro Santos, Jorge Guilherme, Nuno Horta:
11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology. PRIME 2018: 29-32 - [c25]António Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço, Jorge Guilherme, Nuno Horta:
A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications. SMACD 2018: 1-4 - 2017
- [c24]Jose Cachaco, Nuno Machado, Nuno Lourenço, Jorge Guilherme, Nuno Horta:
Automatic technology migration of analog IC designs using generic cell libraries. DATE 2017: 1281-1284 - [c23]Jonathan Calvillo, Jorge Guilherme, Nuno Horta:
Design of a BGR Suitable for the Space Industry with Performance of 1.25 V with 0.758 ppm/°C TC from - 55° to 125°C. NGCAS 2017: 197-200 - 2016
- [j6]Mauro Santos, Nuno Horta, Jorge Guilherme:
Logarithmic AD Converter With Selectable Transfer Characteristic. IEEE Trans. Circuits Syst. II Express Briefs 63-II(3): 234-238 (2016) - [c22]Carlos Silva, Jorge Guilherme, Nuno Horta:
SCALES: A high speed simulator tool for pipeline A/D converters. SMACD 2016: 1-4 - 2015
- [c21]David Guilherme, João Pereira, Nuno Horta, Jorge Guilherme:
Thermal-aware floorplanning and layout generation of MOSFET power stages. ISCAS 2015: 2269-2272 - 2014
- [j5]Mauro Santos, Nuno Horta, Jorge Guilherme:
A survey on nonlinear analog-to-digital converters. Integr. 47(1): 12-22 (2014) - [c20]Mauro Santos, Nuno Horta, Jorge Guilherme:
Logarithmic AD conversion using latched comparators and a time-to-digital converter. ICECS 2014: 319-322 - [c19]Bruno Silva, Nuno Horta, Jorge Guilherme:
A rad-hard DC-DC converter controller. ICECS 2014: 439-442 - [c18]David Guilherme, Nuno Horta, Jorge Guilherme:
Automatic layout generation of power MOSFET transistors in bulk CMOS. ICECS 2014: 606-609 - 2011
- [c17]Frederico Cadete, David Guilherme, Jorge Guilherme, Nuno Horta:
Overcurrent detection circuit for integrated class-D amplifiers. ECCTD 2011: 401-404 - [c16]Pedro Sousa, Carla Duarte, Manuel F. M. Barros, Jorge Guilherme, Nuno Horta:
Optimal OpAmp sizing based on a fuzzy-genetic kernel. GECCO (Companion) 2011: 827-828 - 2010
- [b1]Manuel F. M. Barros, Jorge M. C. Guilherme, Nuno C. G. Horta:
Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques. Studies in Computational Intelligence 294, Springer 2010, ISBN 978-3-642-12345-0 - [j4]Manuel F. M. Barros, Jorge Guilherme, Nuno Horta:
Analog circuits optimization based on evolutionary computation techniques. Integr. 43(1): 136-155 (2010)
2000 – 2009
- 2009
- [j3]Artur Silva, Jorge Guilherme, Nuno Horta:
Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals. Integr. 42(1): 34-46 (2009) - [j2]Jongwoo Lee, Joshua Jaeyoung Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn:
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. IEEE J. Solid State Circuits 44(10): 2755-2765 (2009) - [c15]Alexandre Ribeiro, António Sirgado, João Aperta, Ana C. Lopes, Jorge Guilherme, Pedro D. F. Correia, Gabriel Pires, Urbano Nunes:
A Low-cost EEG Stand-alone Device for Brain Computer Interface. BIODEVICES 2009: 430-433 - [c14]Pedro Sousa, Carla Duarte, Manuel F. M. Barros, Jorge Guilherme, Nuno Horta:
Enhancing analog IC design optimization kernels with simple fuzzy models. ECCTD 2009: 775-778 - 2008
- [c13]Mauro Santos, Carlos Pires, Jorge Guilherme, Nuno Horta:
Overview of radiation effects and design constraints off fully custom SMPS. APCCAS 2008: 372-375 - [c12]Artur Silva, Nuno Horta, Jorge Guilherme:
A reconfigurable A/D converter for 4G wireless systems. ISCAS 2008: 924-927 - 2007
- [c11]Manuel F. M. Barros, Jorge Guilherme, Nuno Horta:
An evolutionary optimization kernel using a dynamic GA-SVM model applied to analog IC design. ECCTD 2007: 32-35 - [c10]Artur Silva, Nuno Horta, Jorge Guilherme:
Design of a multimode reconfigurable sigma-delta converter for 4G wireless receivers. ECCTD 2007: 132-135 - [c9]Manuel F. M. Barros, Jorge Guilherme, Nuno Horta:
GA-SVM feasibility model and optimization kernel applied to analog IC design automation. ACM Great Lakes Symposium on VLSI 2007: 469-472 - 2006
- [c8]Manuel F. M. Barros, Jorge Guilherme, Nuno Horta:
GA-SVM Optimization Kernel applied to Analog IC Design Automation. ICECS 2006: 486-489 - 2002
- [c7]Jorge Guilherme, João C. Vital, José E. Franca:
A CMOS logarithmic pipeline A/D converter with a dynamic range of 80 dB. ICECS 2002: 193-196 - 2001
- [c6]Jorge Guilherme, João C. Vital, José E. Franca:
A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction. ICECS 2001: 393-396 - [c5]Jorge Guilherme, Pedro M. Figueiredo, Pedro Azevedo, Goncalo Minderico, Antonio Leal, João C. Vital, José E. Franca:
Design considerations for high resolution pipeline ADCs in digital CMOS technology. ICECS 2001: 497-500 - [c4]Jorge Guilherme, Pedro M. Figueiredo, Pedro Azevedo, Goncalo Minderico, Antonio Leal, João C. Vital, José E. Franca:
A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications. ISCAS (1) 2001: 396-399
1990 – 1999
- 1998
- [c3]Jorge Guilherme, Nuno C. G. Horta, José E. Franca:
Symbolic synthesis of non-linear data converters. ICECS 1998: 219-222 - 1995
- [j1]Saulo Finco, Frank Herman Behrens, Jorge Guilherme, Maria Inês Castro Simas, Mário Lança:
Pushing Standard CMOS Technologies into Smart Power Conversion and Amplification. J. Circuits Syst. Comput. 5(3): 455-464 (1995) - [c2]Jorge Guilherme, José E. Franca:
New CMOS Logarithmic A/D Converters Employing Pipeline and Algorithmic Architectures. ISCAS 1995: 529-532 - 1994
- [c1]Jorge Guilherme, José E. Franca:
Digitally-Controlled Analogue Signal Processing and Conversion Techniques Employing a Logarithmic Building Block. ISCAS 1994: 377-380
Coauthor Index
aka: Nuno C. G. Horta
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