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2000 – 2009
- 2006
[j3]Pedro M. Figueiredo, João C. Vital:
Kickback noise reduction techniques for CMOS latched comparators. IEEE Trans. Circuits Syst. II Express Briefs 53-II(7): 541-545 (2006)- [c15]Pedro M. Figueiredo, Paulo Cardoso, Ana Lopes, Carlos Fachada, Naoyuki Hamanishi, Ken Tanabe, João C. Vital:
A 90nm CMOS 1.2v 6b 1GS/s two-step subranging ADC. ISSCC 2006: 2320-2329 - 2004
- [j2]Pedro M. Figueiredo, João C. Vital:
Averaging technique in flash analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(2): 233-253 (2004) - [j1]Pedro M. Figueiredo, João C. Vital:
The MOS capacitor amplifier. IEEE Trans. Circuits Syst. II Express Briefs 51-II(3): 111-115 (2004) - [c14]Pedro M. Figueiredo, João C. Vital:
Termination of averaging networks in flash ADCs. ISCAS (1) 2004: 121-124 - [c13]Pedro M. Figueiredo, João C. Vital:
Low kickback noise techniques for CMOS latched comparators. ISCAS (1) 2004: 537-540 - 2003
- [c12]Pedro M. Figueiredo, João C. Vital:
Analysis of the averaging technique in flash ADCs. ISCAS (1) 2003: 849-852 - 2002
- [c11]Jorge Guilherme
, João C. Vital, José E. Franca:
A CMOS logarithmic pipeline A/D converter with a dynamic range of 80 dB. ICECS 2002: 193-196 - 2001
- [c10]Xu Jingnan, João C. Vital, Nuno Horta:
A Skill-based library for retargetable embedded analog cores. DATE 2001: 768-769 - [c9]Xu Jingnan, J. Serras, M. Oliveira, R. Belo, M. Bugalho, João C. Vital, Nuno Horta, José E. Franca:
IC design automation from circuit level optimization to retargetable layout. ICECS 2001: 95-98 - [c8]Jorge Guilherme, João C. Vital, José E. Franca:
A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction. ICECS 2001: 393-396 - [c7]Jorge Guilherme, Pedro M. Figueiredo, Pedro Azevedo, Goncalo Minderico, Antonio Leal, João C. Vital, José E. Franca:
Design considerations for high resolution pipeline ADCs in digital CMOS technology. ICECS 2001: 497-500 - [c6]Jorge Guilherme, Pedro M. Figueiredo, Pedro Azevedo, Goncalo Minderico, Antonio Leal, João C. Vital, José E. Franca:
A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications. ISCAS (1) 2001: 396-399
1990 – 1999
- 1999
- [c5]José E. Franca, Nuno Horta, M. Pereira, João C. Vital, Rafael Castro-López, Manuel Delgado-Restituto, Francisco V. Fernández, Ángel Rodríguez-Vázquez, J. Ramos, P. Santos:
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design. ICECS 1999: 1679-1683 - 1995
- [c4]João Goes, João C. Vital, José E. Franca:
Optimum Resolution-per-Stage in High-Speed Pipelined A/D Converters Using Self-Calibration. ISCAS 1995: 525-528 - 1993
- [c3]João C. Vital, José E. Franca:
A Concurrent Two-step Flash Analogue-to-digital Converter Architecture. ISCAS 1993: 1196-1199 - [c2]João C. Vital, José E. Franca, Nuno S. Silva:
Fully-digital Testability of a High-speed Conversion System. ISCAS 1993: 1595-1598 - [c1]João C. Vital, José E. Franca:
High-Speed A/D-D/A Conversion System with Flexible Testing Capabilities. VLSI Design 1993: 357-362
Coauthor Index
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