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ORCIDTakamoto Watanabe
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2020 – today
- 2021
[c15]Takamoto Watanabe:
All-Digital VCO-ADC TAD Using 4CKES-Type in 16-nm FinFET CMOS for Technology Scaling With Stochastic-ADC Method. ICECS 2021: 1-4- [c14]Takamoto Watanabe:
All-Digital VCO-ADC TAD Confirming Scaling and Stochastic Effects Using 16-nm FinFET CMOS. ICECS 2021: 1-4
2010 – 2019
- 2018
- [c13]Takamoto Watanabe:
All-Digital-Very-Scalable-ADC TAD Showing Scaling-Effect in 40/16nm-CMOS Technology. ICECS 2018: 105-108 - 2017
- [c12]Takamoto Watanabe, Hideaki Ishihara, Tomoyasu Ito:
Sensor/RF digitization for IoT-applications using all-digital-very-scalable-ADC TAD. MIXDES 2017: 35-40 - 2015
- [j6]Yu Hou, Takamoto Watanabe, Masaya Miyahara
, Akira Matsuzawa:
An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(2): 466-475 (2015) - [c11]Shigenori Yamauchi, Takamoto Watanabe:
All-digital MEMS tuning-fork self-excited vibration control by phase-relation using TAD-based ADPLL. NEWCAS 2015: 1-4 - 2014
- [c10]Takamoto Watanabe, Yu Hou, Masaya Miyahara, Akira Matsuzawa:
All-digital 0.016mm2 reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS. ICECS 2014: 21-24 - [c9]Tomohito Terasawa, Yuji Kamiya, Hiroyuki Kawashima, Kenichiro Imai, Masanobu Suzuki, Takamoto Watanabe, Nobuyuki Taguchi, Manabu Sawada, Yu Hou, Yoshiyuki Hirooka, Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa:
Radio receiver front-end using time-based all-digital ADC (TAD). ICECS 2014: 471-473 - [c8]Takamoto Watanabe, Hirofumi Isomura:
All-digital ADC/TDC using TAD architecture for highly-durable time-measurement ASIC. ISCAS 2014: 674-677 - 2012
- [c7]Takamoto Watanabe, Hirofumi Isomura, Tomohito Terasawa:
All-Digital A/D converter TAD for sensor interface over wide temperature ranges. ICECS 2012: 117-120 - [c6]Takamoto Watanabe, Tomohito Terasawa:
All-digital A/D converter TAD for high-resolution and low-power sensor/RF interface. ICECS 2012: 197-200 - 2010
- [c5]Takamoto Watanabe, Tomohito Terasawa:
An all-digital A/D converter TAD with 4-shift-clock construction for sensor interface in 0.65-μm CMOS. ESSCIRC 2010: 178-181 - [c4]Takamoto Watanabe, Tomohito Terasawa:
All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection. ICECS 2010: 786-789
2000 – 2009
- 2009
- [j5]Sumio Masuda, Takamoto Watanabe, Shigenori Yamauchi, Tomohito Terasawa:
All-Digital Quadrature Detection With TAD for Radio-Controlled Clocks/Watches. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 285-293 (2009) - [c3]Takamoto Watanabe, Tomohito Terasawa:
An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS. ICECS 2009: 219-222 - [c2]Takamoto Watanabe, Shigenori Yamauchi, Tomohito Terasawa:
A 0.0027-mm2 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS. ICECS 2009: 271-274 - 2003
- [j4]Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering. IEEE J. Solid State Circuits 38(1): 120-125 (2003) - [j3]Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
DC-coupled IF stage design for a 900-MHz ISM receiver. IEEE J. Solid State Circuits 38(1): 126-134 (2003) - [j2]Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology. IEEE J. Solid State Circuits 38(1): 135-137 (2003) - [j1]Takamoto Watanabe, Shigenori Yamauchi:
An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time. IEEE J. Solid State Circuits 38(2): 198-204 (2003) - 2001
- [c1]Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
A 14-bit 12 μV/LSB resolution A/D converter for sensors using only digital circuit with low-pass filter effect. ICECS 2001: 677-680
Coauthor Index
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