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ORCIDGeorges G. E. Gielen
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- affiliation: Catholic University of Leuven, Belgium
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2020 – today
- 2024
[j129]Jonah Van Assche
, Georges G. E. Gielen:
Analysis and Design of a 10.4-ENOB 0.92-5.38-μW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications. IEEE J. Solid State Circuits 59(9): 2858-2869 (2024)- [j128]Ali Safa, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen:
STDP-Driven Development of Attention-Based People Detection in Spiking Neural Networks. IEEE Trans. Cogn. Dev. Syst. 16(1): 380-387 (2024) - [j127]Marco Francesco Carlino, Georges G. E. Gielen:
Brain Feature Extraction With an Artifact-Tolerant Multiplexed Time-Encoding Neural Frontend for True Real-Time Closed-Loop Neuromodulation. IEEE Trans. Biomed. Circuits Syst. 18(3): 511-522 (2024) - [j126]Mark Daniel Alea, Ali Safa, Flavio Giacomozzi, Andrea Adami, Inci Rüya Temel, Maria Atalaia Rosa, Leandro Lorenzelli, Georges G. E. Gielen:
A Fingertip-Mimicking 12$\times$16 200 $\mu$m-Resolution e-Skin Taxel Readout Chip With Per-Taxel Spiking Readout and Embedded Receptive Field Processing. IEEE Trans. Biomed. Circuits Syst. 18(6): 1308-1320 (2024) - [c275]Mohsen Ahmadzadeh, Georges G. E. Gielen:
Using Probabilistic Model Rollouts to Boost the Sample Efficiency of Reinforcement Learning for Automated Analog Circuit Sizing. DAC 2024: 295:1-295:6 - [c274]Kaichang Chen, Georges G. E. Gielen:
Self-Learning and Transfer Across Topologies of Constraints for Analog / Mixed-Signal Circuit Layout Synthesis. DATE 2024: 1-6 - [c273]Erik Jan Marinissen, Harish Dattatraya Dixit, Ronald Shawn Blanton, Aaron Kuo, Wei Li, Subhasish Mitra, Chris Nigh, Ruben Purdy, Ben Kaczer, Dishant Sangani, Pieter Weckx, Philippe J. Roussel, Georges G. E. Gielen:
Silent Data Corruption: Test or Reliability Problem? ETS 2024: 1-7 - [c272]Dishant Sangani, Ben Kaczer, Pieter Weckx, Philippe J. Roussel, Subrat Mishra, Erik Jan Marinissen, Georges G. E. Gielen:
Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers. IRPS 2024: 1-7 - [c271]Pablo Saraza-Canflanca, Dishant Sangani, Javier Diaz-Fortuny, Stanislav Tyaginov, Georges G. E. Gielen, Erik Bury, Ben Kaczer:
Statistical Characterization of Off-State Stress Degradation in Planar HKMG nFETs Using Device Arrays. IRPS 2024: 8 - [c270]Xinpeng Gui, Xinfa Zheng, Haigang Feng, Georges G. E. Gielen, Zhihua Wang, Xinpeng Xing:
A 70dB SNDR 20MHz-BW VCO-Based CT Sturdy MASH Delta-Sigma Modulator with Robust Quantization Error Extraction. ISCAS 2024: 1-5 - [c269]Ali Safa, Vikrant Jaltare, Samira Sebt, Kameron Gano, Johannes Leugering, Georges G. E. Gielen, Gert Cauwenberghs:
Towards Chip-in-the-loop Spiking Neural Network Training via Metropolis-Hastings Sampling. NICE 2024: 1-5 - [c268]Xiaohua Huang, Xiaolin Yang, Andrea Lodi, Chris Van Hoof, Georges G. E. Gielen, Carolina Mora Lopez:
A 3072-Channel Neural Readout IC with Multiplexed Two-Step Incremental-SAR Conversion and Bulk-DAC-Based EDO Compensation in 22nm FDSOI. VLSI Technology and Circuits 2024: 1-2 - [i11]Ali Safa, Vikrant Jaltare, Samira Sebt, Kameron Gano, Johannes Leugering, Georges G. E. Gielen, Gert Cauwenberghs:
Towards Chip-in-the-loop Spiking Neural Network Training via Metropolis-Hastings Sampling. CoRR abs/2402.06284 (2024) - 2023
- [j125]Yingping Chen, Bernardo Tacca, Yunzhu Chen, Dwaipayan Biswas, Georges G. E. Gielen, Francky Catthoor, Marian Verhelst, Carolina Mora Lopez:
An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing. IEEE J. Solid State Circuits 58(11): 2990-3002 (2023) - [j124]Nektar Xama, Jhon Gomez, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Georges G. E. Gielen:
Boosting Latent Defect Coverage in Automotive Mixed-Signal ICs Using SVM Classifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3426-3435 (2023) - [j123]Aurojyoti Das, Qiuyang Lin, Sybren Santermans, Lijun Liu, Chris Van Hoof, Georges G. E. Gielen, Nick Van Helleputte:
High-Throughput Nanopore-FET Array Readout IC With 5-MHz Bandwidth and Background Offset/Drift Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4323-4333 (2023) - [j122]Leidy Mabel Alvero-Gonzalez, Georges G. E. Gielen, Eric Gutierrez:
Delay Cell for Highly-Linear Current-Controlled Oscillator-Based Analog-to-Digital Conversion. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3238-3242 (2023) - [j121]Ali Safa, Federico Corradi, Lars Keuninckx, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen:
Improving the Accuracy of Spiking Neural Networks for Radar Gesture Recognition Through Preprocessing. IEEE Trans. Neural Networks Learn. Syst. 34(6): 2869-2881 (2023) - [c267]Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC 2023: 1-6 - [c266]Jonah Van Assche, Marco Francesco Carlino, Mark Daniel Alea, Sergio Massaioli, Georges G. E. Gielen:
From sensor to inference: end-to-end chip design for wearable and implantable biomedical applications. BioCAS 2023: 1-5 - [c265]Marco Francesco Carlino, Sergio Massaioli, Georges G. E. Gielen:
Highly-Digital 0.0018-mm2/channel Multiplexed Neural Frontend with Time-Based Incremental ADC for In-Brain-Stroke-Cavity LFP Monitoring. BioCAS 2023: 1-5 - [c264]Jiaqi Wang, Mark Daniel Alea, Jonah Van Assche, Georges G. E. Gielen:
End-to-End Optimization of High-Density e-Skin Design: From Spiking Taxel Readout to Texture Classification. DATE 2023: 1-6 - [c263]Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen:
High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis. ETS 2023: 1-4 - [c262]Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen:
Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. ETS 2023: 1-6 - [c261]Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen:
Fusing Event-based Camera and Radar for SLAM Using Spiking Neural Networks with Continual STDP Learning. ICRA 2023: 2782-2788 - [c260]Dishant Sangani, Javier Diaz-Fortuny, Erik Bury, Ben Kaczer, Georges G. E. Gielen:
The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper). IRPS 2023: 1-6 - [c259]Yingping Chen, Bernardo Tacca, Yunzhu Chen, Dwaipayan Biswas, Georges G. E. Gielen, Francky Catthoor, Marian Verhelst, Carolina Mora Lopez:
A 384-Channel Online-Spike-Sorting IC Using Unsupervised Geo-OSort Clustering and Achieving 0.0013mm2/Ch and $1.78\mu \text{W/ch}$. ISSCC 2023: 486-487 - [c258]Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen:
Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. ITC 2023: 151-158 - [c257]Ali Safa, Tim Verbelen, Lars Keuninckx, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen, Gert Cauwenberghs:
Active Inference in Hebbian Learning Networks. IWAI 2023: 239-253 - [c256]Georges G. E. Gielen:
Neuromorphic computing in the edge: merging cyber and physical. IWASI 2023: 286 - [c255]Georges G. E. Gielen:
Analog synthesis 3.0: AI/ML to synthesize and test analog ICs: hope or hype ? MLCAD 2023: 1 - [c254]Ali Safa, Ilja Ocket, Francky Catthoor, Georges G. E. Gielen:
SupportHDC: Hyperdimensional Computing with Scalable Hypervector Sparsity. NICE 2023: 20-25 - [c253]Ali Safa, Jonah Van Assche, Charlotte Frenkel, André Bourdoux, Francky Catthoor, Georges G. E. Gielen:
Exploring Information-Theoretic Criteria to Accelerate the Tuning of Neuromorphic Level-Crossing ADCs. NICE 2023: 63-70 - [c252]Mark Daniel Alea, Ali Safa, Flavio Giacomozzi, Andrea Adami, Inci Rüya Temel, Leandro Lorenzelli, Georges G. E. Gielen:
A Fingertip-Mimicking 12×16 200μm-Resolution e-skin Taxel Readout Chip with per-Taxel Spiking Readout and Embedded Receptive Field Processing. VLSI Technology and Circuits 2023: 1-2 - [c251]Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS 2023: 1-6 - [i10]Ali Safa, Tim Verbelen, Lars Keuninckx, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen, Gert Cauwenberghs:
Active Inference in Hebbian Learning Networks. CoRR abs/2306.05053 (2023) - 2022
- [j120]Benjamin Gys, Rohith Acharya, Steven Van Winckel, Kristiaan De Greve, Georges G. E. Gielen, Francky Catthoor:
A Co-Simulation Methodology for the Design of Integrated Silicon Spin Qubits With Their Control/Readout Cryo-CMOS Electronics. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(3): 685-693 (2022) - [j119]Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
A 96.9-dB-Resolution 109-μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed Single-Ended Resistance Readout in 180-nm CMOS. IEEE J. Solid State Circuits 57(9): 2764-2777 (2022) - [j118]Xiaohua Huang, Horacio Londoño-Ramírez, Marco Ballini, Chris Van Hoof, Jan Genoe, Sebastian Haesler, Georges G. E. Gielen, Nick Van Helleputte, Carolina Mora Lopez:
Actively Multiplexed μECoG Brain Implant System With Incremental-ΔΣ ADCs Employing Bulk-DACs. IEEE J. Solid State Circuits 57(11): 3312-3323 (2022) - [j117]Ali Safa, Jonah Van Assche, Mark Daniel Alea, Francky Catthoor, Georges G. E. Gielen:
Neuromorphic Near-Sensor Computing: From Event-Based Sensing to Edge Learning. IEEE Micro 42(6): 88-95 (2022) - [j116]Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen:
Fail-Safe Human Detection for Drones Using a Multi-Modal Curriculum Learning Approach. IEEE Robotics Autom. Lett. 7(1): 303-310 (2022) - [j115]Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen:
DDtM: Increasing Latent Defect Detection in Analog/Mixed-Signal ICs Using the Difference in Distance to Mean Value. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4771-4781 (2022) - [j114]Jonas Borgmans, Elisa Sacco, Pieter Rombouts, Georges G. E. Gielen:
Methodology for Readout and Ring Oscillator Optimization Toward Energy-Efficient VCO-Based ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 985-998 (2022) - [j113]Xiaohua Huang, Marco Ballini, Shiwei Wang, Beatrice Miccoli, Chris Van Hoof, Georges G. E. Gielen, Jan Craninckx, Nick Van Helleputte, Carolina Mora Lopez:
A Compact, Low-Power Analog Front-End With Event-Driven Input Biasing for High-Density Neural Recording in 22-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 804-808 (2022) - [c250]Zhanpeng Yang, Xinpeng Xing, Xinfa Zheng, Haigang Feng, Hongyan Fu, Georges G. E. Gielen:
An 8-b 8-GS/s Time-Interleaved SAR ADC With Foreground Offset Calibration in 28nm CMOS. APCCAS 2022: 181-184 - [c249]Zhikun He, Xinpeng Xing, Xinfa Zheng, Haigang Feng, Hongyan Fu, Georges G. E. Gielen:
Low Power and High Speed Designs of CIC Filter for Sigma-Delta ADCs. APCCAS 2022: 236-240 - [c248]Mark Daniel Alea, Ali Safa, Jonah Van Assche, Georges G. E. Gielen:
Power-Efficient and Accurate Texture Sensing Using Spiking Readouts for High-Density e-Skins. BioCAS 2022: 359-363 - [c247]Jonah Van Assche, Ruben Helsen, Georges G. E. Gielen:
EffiCSense: an Architectural Pathfinding Framework for Energy-Constrained Sensor Applications. DATE 2022: 136-141 - [c246]Jonah Van Assche, Georges G. E. Gielen:
A 10.4-ENOB 0.92-5.38 μW Event-Driven Level-Crossing ADC with Adaptive Clocking for Time-Sparse Edge Applications. ESSCIRC 2022: 261-264 - [c245]Ali Safa, Ilja Ocket, Francky Catthoor, Georges G. E. Gielen:
Exploring Cross-fusion and Curriculum Learning for Multi-modal Human Detection on Drones. DroneSE/RAPIDO@HiPEAC 2022: 1-7 - [c244]Marco Francesco Carlino, Georges G. E. Gielen:
A servo-loop-free charge sharing technique to mitigate electrode offsets in biomedical multiplexed interfaces. ICECS 2022 2022: 1-4 - [c243]Ali Safa, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen:
Event Camera Data Classification Using Spiking Networks with Spike-Timing-Dependent Plasticity. IJCNN 2022: 1-8 - [c242]Xiaohua Huang, Horacio Londoño-Ramírez, Marco Ballini, Chris Van Hoof, Jan Genoe, Sebastian Haesler, Georges G. E. Gielen, Nick Van Helleputte, Carolina Mora Lopez:
A 256-Channel Actively-Multiplexed µECoG Implant with Column-Parallel Incremental ΔΣ ADCs Employing Bulk-DACs in 22-nm FDSOI Technology. ISSCC 2022: 200-202 - [c241]Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen:
Learning to Encode Vision on the Fly in Unknown Environments: A Continual Learning SLAM Approach for Drones. SSRR 2022: 373-378 - [c240]Rohith Acharya, Anton Potocnik, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu:
Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements. VLSI Technology and Circuits 2022: 230-231 - [i9]Ali Safa, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen:
Continuously Learning to Detect People on the Fly: A Bio-inspired Visual System for Drones. CoRR abs/2202.08023 (2022) - [i8]Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen:
Learning to SLAM on the Fly in Unknown Environments: A Continual Learning Approach for Drones in Visually Ambiguous Scenes. CoRR abs/2208.12997 (2022) - [i7]Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen:
Fusing Event-based Camera and Radar for SLAM Using Spiking Neural Networks with Continual STDP Learning. CoRR abs/2210.04236 (2022) - 2021
- [j112]Hui Liu, Xinpeng Xing, Georges G. E. Gielen:
A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS. IEEE J. Solid State Circuits 56(1): 287-297 (2021) - [j111]Ali Safa, Francky Catthoor, Georges G. E. Gielen:
ConvSNN: A surrogate gradient spiking neural framework for radar gesture recognition. Softw. Impacts 10: 100131 (2021) - [j110]Ali Safa, Tim Verbelen, Lars Keuninckx, Ilja Ocket, Matthias Hartmann, André Bourdoux, Francky Catthoor, Georges G. E. Gielen:
A Low-Complexity Radar Detector Outperforming OS-CFAR for Indoor Drone Obstacle Avoidance. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 14: 9162-9175 (2021) - [j109]Nicolas Callens, Georges G. E. Gielen:
Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3117-3130 (2021) - [c239]Rohith Acharya, Fahd A. Mohiyaddin, Anton Potocnik, Kristiaan De Greve, Bogdan Govoreanu, Iuliana P. Radu, Georges G. E. Gielen, Francky Catthoor:
Circuit models for the co-simulation of superconducting quantum computing systems. DATE 2021: 968-973 - [c238]Benjamin Gys, Fahd A. Mohiyaddin, Rohith Acharya, Roy Li, Kristiaan De Greve, Georges G. E. Gielen, Bogdan Govoreanu, Iuliana P. Radu, Francky Catthoor:
Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. ESSCIRC 2021: 63-66 - [c237]Benjamin Gys, Fahd A. Mohiyaddin, Rohith Acharya, Roy Li, Kristiaan De Greve, Georges G. E. Gielen, Bogdan Govoreanu, Iuliana P. Radu, Francky Catthoor:
Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. ESSDERC 2021: 63-66 - [c236]Xinpeng Xing, Xueqian Shang, Senji Liu, Xinfa Zheng, Georges G. E. Gielen:
Power-efficient VCO-based ADCs for Wireless Communication Systems. ISOCC 2021: 244-245 - [i6]Koen Bertels, Aritra Sarkar, Anna M. Krol, Ravish Budhrani, J. Samadi, E. Geoffroy, J. Matos, R. Abreu, Georges G. E. Gielen, Imran Ashraf:
Quantum Accelerator Stack: A Research Roadmap. CoRR abs/2102.02035 (2021) - [i5]Ali Safa, Tim Verbelen, Lars Keuninckx, Ilja Ocket, Matthias Hartmann, André Bourdoux, Francky Catthoor, Georges G. E. Gielen:
A Low-Complexity Radar Detector Outperforming OS-CFAR for Indoor Drone Obstacle Avoidance. CoRR abs/2107.07250 (2021) - [i4]Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen:
Fail-Safe Human Detection for Drones Using a Multi-Modal Curriculum Learning Approach. CoRR abs/2109.13666 (2021) - [i3]Ali Safa, Hichem Sahli, André Bourdoux, Ilja Ocket, Francky Catthoor, Georges G. E. Gielen:
Learning Event-based Spatio-Temporal Feature Descriptors via Local Synaptic Plasticity: A Biologically-realistic Perspective of Computer Vision. CoRR abs/2111.00791 (2021) - 2020
- [j108]Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
A 16.1-bit Resolution 0.064-mm2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS. IEEE J. Solid State Circuits 55(9): 2456-2467 (2020) - [j107]Jonah Van Assche, Georges G. E. Gielen:
Power Efficiency Comparison of Event-Driven and Fixed-Rate Signal Conversion and Compression for Biomedical Applications. IEEE Trans. Biomed. Circuits Syst. 14(4): 746-756 (2020) - [j106]Hui Liu, Pieter Rombouts, Georges G. E. Gielen:
Efficient Offline Outer/Inner DAC Mismatch Calibration in Wideband ΔΣ ADCs. IEEE Trans. Circuits Syst. 67-I(12): 4259-4269 (2020) - [j105]Nektar Xama, Martin Andraud, Jhon Gomez, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Georges G. E. Gielen:
Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations. ACM Trans. Design Autom. Electr. Syst. 25(5): 47:1-47:27 (2020) - [c235]Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Nektar Xama, Jhon Gomez, Georges G. E. Gielen:
Latent Defect Screening with Visually-Enhanced Dynamic Part Average Testing. ETS 2020: 1-6 - [c234]Nektar Xama, Jakob Raymaekers, Martin Andraud, Jhon Gomez, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Georges G. E. Gielen:
Avoiding Mixed-Signal Field Returns by Outlier Detection of Hard-to-Detect Defects based on Multivariate Statistics. ETS 2020: 1-6 - [c233]Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
Improving the EMI Robustness of Feedback-based Time-Encoding Readout Architectures for Resistive Sensor Interfaces. ICECS 2020: 1-4 - [c232]Stephen Sunter, Michal Wolinski, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Nektar Xama, Jhon Gomez, Georges G. E. Gielen:
Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs. ITC 2020: 1-10 - [c231]Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen:
Pinhole Latent Defect Modeling and Simulation for Defect-Oriented Analog/Mixed-Signal Testing. VTS 2020: 1-6
2010 – 2019
- 2019
- [j104]Jorge Marin, Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
A Robust BBPLL-Based 0.18- $\mu$ m CMOS Resistive Sensor Interface With High Drift Resilience Over a -40 °C-175 °C Temperature Range. IEEE J. Solid State Circuits 54(7): 1862-1873 (2019) - [j103]Elisa Sacco, Jorge Marin, Johan Vergauwen, Georges G. E. Gielen:
Performance Limitation Analysis of Highly-Digital Time-Based Closed-Loop Sensor-to-Digital Converter Architectures. IEEE Trans. Circuits Syst. II Express Briefs 66-II(7): 1114-1118 (2019) - [j102]Hui Liu, Xinpeng Xing, Georges G. E. Gielen:
An 85-MHz-BW ASAR-Assisted CT 4-0 MASH $\Delta\Sigma$ Modulator With Background Half-Range Dithering-Based DAC Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2405-2414 (2019) - [j101]Marko Simicic, Pieter Weckx, Bertrand Parvais, Philippe Roussel, Ben Kaczer, Georges G. E. Gielen:
Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 601-610 (2019) - [c230]Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
A 16.1-b ENOB 0.064mm2 Compact Highly-Digital Closed-Loop Single-VCO-based 1-1 SMASH Resistance-to-Digital Converter in 180nm CMOS. A-SSCC 2019: 109-112 - [c229]Georges G. E. Gielen, Nektar Xama, Karthik Ganesan, Subhasish Mitra:
Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs. DATE 2019: 1006-1009 - [c228]Wim Dobbelaere, Frederik Colle, Anthony Coyette, Ronny Vanhooren, Nektar Xama, Jhon Gomez, Georges G. E. Gielen:
Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs. ITC 2019: 1-4 - [c227]Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
From Open-Loop to Closed-Loop Single-VCO-Based Sensor-to-Digital Converter Architectures: theoretical analysis and comparison. IWASI 2019: 29-34 - [c226]Georges G. E. Gielen:
The fantastic voyage towards ultra-miniaturized sensing circuits. IWASI 2019: 35 - [c225]Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
Architectural Analysis of a Novel Closed-Loop VCO-Based 1-1 Sturdy MASH Sensor-to-Digital Converter. SMACD 2019: 261-264 - 2018
- [j100]Mai O. Sallam, Guy A. E. Vandenbosch, Georges G. E. Gielen, Ezzeldin A. Soliman:
Generalized mode solver for plasmonic transmission lines embedded in layered media based on the Method of Moments. Comput. Phys. Commun. 233: 1-15 (2018) - [j99]Baris Esen, Anthony Coyette, Nektar Xama, Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren:
An Automated Low-Cost Analog and Mixed-Signal DfT Method Using Testing Diodes. IEEE Des. Test 35(3): 15-23 (2018) - [j98]Anthony Coyette, Baris Esen, Nektar Xama, Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren:
ADAGE: Automatic DfT-Assisted Generation of Test Stimuli for Mixed- Signal Integrated Circuits. IEEE Des. Test 35(3): 24-30 (2018) - [j97]Ha Le-Thai, Genis Chapinal, Tomas Geurts, Georges G. E. Gielen:
A 0.18-µm CMOS Image Sensor With Phase-Delay-Counting and Oversampling Dual-Slope Integrating Column ADCs Achieving 1e-rms Noise at 3.8-µs Conversion Time. IEEE J. Solid State Circuits 53(2): 515-526 (2018) - [c224]Hui Liu, Xinpeng Xing, Georges G. E. Gielen:
An 85MHz-BW 68.5dB-SNDR ASAR-assisted CT 4-0 MASH ΔΣ modulator with half-range dithering-based DAC calibration in 28nm CMOS. CICC 2018: 1-4 - [c223]Jorge Marin, Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
A Single-Temperature-Calibration 0.18-µm CMOS Time-Based Resistive Sensor Interface with Low Drift over a -40°C to 175°C Temperature Range. ESSCIRC 2018: 330-333 - [c222]Georges G. E. Gielen, Jorge Marin, Elisa Sacco:
Improving the robustness and drift resilience of CMOS BBPLL-based time-based sensor interfaces. ICECS 2018: 117-120 - [c221]Georges G. E. Gielen, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Nektar Xama:
Methodology Towards Sub-ppm Testing of Analog and Mixed-Signal ICs for Cyber-Physical Systems. ISCAS 2018: 1-4 - [c220]Elisa Sacco, Jorge Marin, Johan Vergauwen, Georges G. E. Gielen:
Controlled-Oscillator Optimization for Highly-Digital CMOS Time-Based Sensor-to-Digital Converter Architectures. SMACD 2018: 249-252 - 2017
- [j96]Rachit Mohan, Samira Zaliasl, Georges G. E. Gielen, Chris Van Hoof, Refet Firat Yazicioglu, Nick Van Helleputte:
A 0.6-V, 0.015-mm2, Time-Based ECG Readout for Ambulatory Applications in 40-nm CMOS. IEEE J. Solid State Circuits 52(1): 298-308 (2017) - [c219]Xinpeng Xing, Peng Zhu, Hui Liu, Wei Wang, Georges G. E. Gielen:
A power-efficient reconfigurable two-step VCO-based ADC for software-defined radio. ASICON 2017: 620-623 - [c218]Baris Esen, Anthony Coyette, Nektar Xama, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen:
A very low cost and highly parallel DfT method for analog and mixed-signal circuits. ETS 2017: 1-2 - [c217]Nektar Xama, Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen:
Automatic testing of analog ICs for latent defects using topology modification. ETS 2017: 1-6 - [c216]Baris Esen, Anthony Coyette, Nektar Xama, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen:
Non-intrusive detection of defects in mixed-signal integrated circuits using light activation. ITC 2017: 1-7 - [c215]Georges G. E. Gielen, Jorge Marin, Elisa Sacco:
Drift mitigation in integrated sensor interfaces. IWASI 2017: 51 - [c214]Jorge Marin, Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
Analysis and modeling of drift-resilient time-based integrated resistive sensor interfaces. IWASI 2017: 183-186 - 2016
- [j95]Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen:
Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization. Integr. 55: 393-400 (2016) - [j94]Georges G. E. Gielen, Jelle Van Rethy, Jorge Marin, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra:
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 577-586 (2016) - [c213]Bo Liu, Nan Sun, Qingfu Zhang, Vic Grout, Georges G. E. Gielen:
A surrogate model assisted evolutionary algorithm for computationally expensive design optimization problems with discrete variables. CEC 2016: 1650-1657 - [c212]Ha Le-Thai, Adi Xhakoni, Georges G. E. Gielen:
A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniques. ESSCIRC 2016: 221-224 - [c211]Rachit Mohan, Samira Zaliasl, Georges G. E. Gielen, Chris Van Hoof, Nick Van Helleputte, Refet Firat Yazicioglu:
28.5 A 0.6V 0.015mm2 time-based biomedical readout for ambulatory applications in 40nm CMOS. ISSCC 2016: 482-483 - [c210]Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen:
Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis. ITC 2016: 1-10 - [c209]Wim Dobbelaere, Ronny Vanhooren, Willy De Man, Koen Matthijs, Anthony Coyette, Baris Esen, Georges G. E. Gielen:
Analog fault coverage improvement using final-test dynamic part average testing. ITC 2016: 1-9 - [c208]Baris Esen, Anthony Coyette, Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren:
Effective DC fault models and testing approach for open defects in analog circuits. ITC 2016: 1-9 - 2015
- [j93]Xinpeng Xing, Georges G. E. Gielen:
A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS. IEEE J. Solid State Circuits 50(3): 714-723 (2015) - [j92]Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene:
Development of an Ultralow-Power Injection-Locked PSK Receiver Architecture. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 31-35 (2015) - [j91]Peng Zhu, Xinpeng Xing, Georges G. E. Gielen:
A 40-MHz Bandwidth 0-2 MASH VCO-Based Delta-Sigma ADC With 35-fJ/Step FoM. IEEE Trans. Circuits Syst. II Express Briefs 62-II(10): 952-956 (2015) - [c207]Xinpeng Xing, Gaozhan Cai, Georges G. E. Gielen:
A lowpass/bandpass reconfigurable continuous-time ΔΣ ADC for software-defined radio. ASICON 2015: 1-4 - [c206]Anthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen:
Automatic generation of autonomous built-in observability structures for analog circuits. ETS 2015: 1-6 - [c205]Iman Khajenasiri, Joseph Virgone, Georges G. E. Gielen:
A presence-based control strategy solution for HVAC systems. ICCE 2015: 620-622 - [c204]Georges G. E. Gielen, Jelle Van Rethy, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra:
Time-based sensor interface circuits in carbon nanotube technology. ISCAS 2015: 2924-2927 - [c203]Georges G. E. Gielen:
Design of low-power sensor interfaces in the IoT era. IWASI 2015: 173 - [c202]Anthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen:
Automated testing of mixed-signal integrated circuits by topology modification. VTS 2015: 1-6 - 2014
- [b2]Bo Liu, Georges G. E. Gielen, Francisco V. Fernández:
Automated Design of Analog and High-frequency Circuits - A Computational Intelligence Approach. Studies in Computational Intelligence 501, Springer 2014, ISBN 978-3-642-39161-3, pp. 1-235 - [j90]Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hai Wei, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs. IEEE J. Solid State Circuits 49(1): 190-201 (2014) - [j89]Carolina Mora Lopez, Alexandru Andrei, Srinjoy Mitra, Marleen Welkenhuysen, Wolfgang Eberle, Carmen Bartic, Robert Puers, Refet Firat Yazicioglu, Georges G. E. Gielen:
An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe. IEEE J. Solid State Circuits 49(1): 248-261 (2014) - [j88]Jelle Van Rethy, Hans Danneels, Georges G. E. Gielen:
Scalable Bang-Bang Phase-Locked-Loop-based integrated sensor interfaces. Microelectron. J. 45(12): 1641-1647 (2014) - [j87]Vladimir Ceperic, Georges G. E. Gielen, Adrijan Baric:
Sparse ε-tube support vector regression by active learning. Soft Comput. 18(6): 1113-1126 (2014) - [j86]Bo Liu, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen:
GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 169-182 (2014) - [j85]Adi Xhakoni, Georges G. E. Gielen:
A 132-dB Dynamic-Range Global-Shutter Stacked Architecture for High-Performance Imagers. IEEE Trans. Circuits Syst. II Express Briefs 61-II(6): 398-402 (2014) - [j84]Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene:
Transient Behavior and Phase Noise Performance of Pulsed-Harmonic Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2119-2128 (2014) - [j83]Bo Liu, Qingfu Zhang, Georges G. E. Gielen:
A Gaussian Process Surrogate Model Assisted Evolutionary Algorithm for Medium Scale Expensive Optimization Problems. IEEE Trans. Evol. Comput. 18(2): 180-192 (2014) - [c201]Ivo Bolsens, Georges G. E. Gielen, Kaushik Roy, Ulf Schneider:
"All Programmable SOC FPGA for networking and computing in big data infrastructure". ASP-DAC 2014: 1-3 - [c200]Bo Liu, Qin Chen, Qingfu Zhang, Georges G. E. Gielen, Vic Grout:
Behavioral study of the surrogate model-aware evolutionary search framework. IEEE Congress on Evolutionary Computation 2014: 715-722 - [c199]Mengyuan Wu, Ammar Karkar, Bo Liu, Alex Yakovlev, Georges G. E. Gielen, Vic Grout:
Network on Chip optimization based on surrogate model assisted evolutionary algorithms. IEEE Congress on Evolutionary Computation 2014: 3266-3271 - [c198]Peng Zhu, Xinpeng Xing, Georges G. E. Gielen:
A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer. ESSCIRC 2014: 63-66 - [c197]Anthony Coyette, Georges G. E. Gielen, Ronny Vanhooren, Wim Dobbelaere:
Optimization of analog fault coverage by exploiting defect-specific masking. ETS 2014: 1-6 - [c196]Iman Khajenasiri, Edoardo Patti, Marco Jahn, Andrea Acquaviva, Marian Verhelst, Enrico Macii, Georges G. E. Gielen:
Design and implementation of a multi-standard event-driven energy management system for smart buildings. GCCE 2014: 20-21 - [c195]Dimitri de Jonghe, Georges G. E. Gielen, Renaud Gillon:
Automatic generation of electro-thermal models with TRAPPIST. ICECS 2014: 842-845 - [c194]Florian De Roose, Valentijn De Smedt, Wouter Volkaerts, Michiel Steyaert, Georges G. E. Gielen, Patrick Reynaert, Wim Dehaene:
Design of a frequency reference based on a PVT-independent transmission line delay. ISCAS 2014: 1772-1775 - [c193]Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Baris Esen:
Design and test of analog circuits towards sub-ppm level. ITC 2014: 1-2 - 2013
- [j82]Jelle Van Rethy, Hans Danneels, Valentijn De Smedt, Wim Dehaene, Georges G. E. Gielen:
Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS. IEEE J. Solid State Circuits 48(11): 2618-2627 (2013) - [j81]Thi Kim Thoa Nguyen, Silke Musa, Wolfgang Eberle, Carmen Bartic, Georges G. E. Gielen:
Mixed-signal template-based reduction scheme for stimulus artifact removal in electrical stimulation. Medical Biol. Eng. Comput. 51(4): 449-458 (2013) - [j80]Jelle Van Rethy, Hans Danneels, Georges G. E. Gielen:
Performance Analysis of Energy-Efficient BBPLL-Based Sensor-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2130-2138 (2013) - [j79]Maarten De Bock, Xinpeng Xing, Ludo Weyten, Georges G. E. Gielen, Pieter Rombouts:
Calibration of DAC Mismatch Errors in ΣΔ ADCs Based on a Sine-Wave Measurement. IEEE Trans. Circuits Syst. II Express Briefs 60-II(9): 567-571 (2013) - [j78]Bo Liu, Qingfu Zhang, Francisco V. Fernández, Georges G. E. Gielen:
An Efficient Evolutionary Algorithm for Chance-Constrained Bi-Objective Stochastic Optimization. IEEE Trans. Evol. Comput. 17(6): 786-796 (2013) - [j77]Soheil Radiom, Majid Baghaei Nejad, Hadi Aliakbarian, Li-Rong Zheng, Guy A. E. Vandenbosch, Georges G. E. Gielen:
Miniaturization of UWB Antennas and its Influence on Antenna-Transceiver Performance in Impulse-UWB Communication. Wirel. Pers. Commun. 71(4): 2913-2935 (2013) - [c192]Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Sacha: the Stanford carbon nanotube controlled handshaking robot. DAC 2013: 124:1-124:3 - [c191]Georges G. E. Gielen, Elie Maricau:
Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS. DATE 2013: 326-331 - [c190]Jelle Van Rethy, Hans Danneels, Valentijn De Smedt, Wim Dehaene, Georges G. E. Gielen:
A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks. DATE 2013: 1431-1435 - [c189]Dimitri de Jonghe, Dirk Deschrijver, Tom Dhaene, Georges G. E. Gielen:
Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories. DATE 2013: 1448-1453 - [c188]Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene:
A 40nm-CMOS, 72 µW injection-locked timing reference and 1.8 Mbit/s coordination receiver for wireless sensor networks. ESSCIRC 2013: 307-310 - [c187]Xinpeng Xing, Peng Gao, Georges G. E. Gielen:
A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS. ESSCIRC 2013: 327-330 - [c186]Jan Verveckken, Frederik Geth, Borbála Hunyadi, Jef Beerten, Niels Leemput, Juan Van Roy, Pieter Tielens, Valentijn De Smedt, Sandro Iacovella, Ninah Koolen, Hans De Clercq, Johan Driesen, Georges G. E. Gielen, Robert Puers, Joos Vandewalle, Sabine Van Huffel, Ronnie Belmans, Geert Deconinck, Wim Dehaene:
Developing engineering-oriented educational workshops within a student branch. EUROCON 2013: 933-940 - [c185]Swaraj Mahato, Georges G. E. Gielen:
Impact of transistor aging on RF low noise amplifier performance of 28nm technology: Reliability assessment. ICECS 2013: 413-416 - [c184]Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs. ISSCC 2013: 112-113 - [c183]Carolina Mora Lopez, Alexandru Andrei, Srinjoy Mitra, Marleen Welkenhuysen, Wolfgang Eberle, Carmen Bartic, Robert Puers, Refet Firat Yazicioglu, Georges G. E. Gielen:
An implantable 455-active-electrode 52-channel CMOS neural probe. ISSCC 2013: 288-289 - [c182]Georges G. E. Gielen:
Timing-based integrated sensor interfaces: Hype or promise? IWASI 2013: 161 - [c181]Vladimir Ceperic, Georges G. E. Gielen, Adrijan Baric:
Black-Box Modelling of AC-DC Rectifiers for RFID Applications Using Support Vector Regression Machines. UKSim 2013: 815-819 - 2012
- [j76]Vladimir Ceperic, Georges G. E. Gielen, Adrijan Baric:
Recurrent sparse support vector regression machines trained by active learning in the time-domain. Expert Syst. Appl. 39(12): 10933-10942 (2012) - [j75]Vladimir Ceperic, Georges G. E. Gielen, Adrijan Baric:
Sparse multikernel support vector regression machines trained by active learning. Expert Syst. Appl. 39(12): 11029-11035 (2012) - [j74]Pieter De Wit, Georges G. E. Gielen:
Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS. IEEE J. Solid State Circuits 47(7): 1757-1767 (2012) - [j73]Carolina Mora Lopez, Dimiter Prodanov, Dries Braeken, Ivan Gligorijevic, Wolfgang Eberle, Carmen Bartic, Robert Puers, Georges G. E. Gielen:
A Multichannel Integrated Circuit for Electrical Recording of Neural Activity, With Independent Channel Programmability. IEEE Trans. Biomed. Circuits Syst. 6(2): 101-110 (2012) - [j72]Bo Liu, Noël Deferm, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen:
An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 981-993 (2012) - [j71]Dimitri de Jonghe, Georges G. E. Gielen:
Characterization of Analog Circuits Using Transfer Function Trajectories. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1796-1804 (2012) - [c180]Bo Liu, Qingfu Zhang, Francisco V. Fernández, Georges G. E. Gielen:
Self-adaptive lower confidence bound: A new general and effective prescreening method for Gaussian Process surrogate model assisted evolutionary algorithms. IEEE Congress on Evolutionary Computation 2012: 1-6 - [c179]Georges G. E. Gielen, Elie Maricau, Pieter De Wit:
Designing reliable analog circuits in an unreliable world. CICC 2012: 1-4 - [c178]Bo Liu, Hadi Aliakbarian, Soheil Radiom, Guy A. E. Vandenbosch, Georges G. E. Gielen:
Efficient multi-objective synthesis for microwave components based on computational intelligence techniques. DAC 2012: 542-548 - [c177]Elie Maricau, Dimitri de Jonghe, Georges G. E. Gielen:
Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection. DATE 2012: 745-750 - [c176]Bo Liu, Jarir Messaoudi, Georges G. E. Gielen:
A fast analog circuit yield estimation method for medium and high dimensional problems. DATE 2012: 751-756 - [c175]Adi Xhakoni, David San Segundo Bello, Georges G. E. Gielen:
Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors. DATE 2012: 836-839 - [c174]Peng Gao, Xinpeng Xing, Jan Craninckx, Georges G. E. Gielen:
Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping. DATE 2012: 1215-1220 - [c173]Dimitri de Jonghe, Elie Maricau, Georges G. E. Gielen, Trent McConaghy, Bratislav Tasic, Haralampos-G. D. Stratigopoulos:
Advances in variation-aware modeling, verification, and testing of analog ICs. DATE 2012: 1615-1620 - [c172]Carolina Mora Lopez, Marleen Welkenhuysen, Silke Musa, Wolfgang Eberle, Carmen Bartic, Robert Puers, Georges G. E. Gielen:
Towards a noise prediction model for in vivo neural recording. EMBC 2012: 759-762 - [c171]Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene:
A 127 μW exact timing reference for Wireless Sensor Networks based on injection locking. ESSCIRC 2012: 262-264 - [c170]Swaraj Mahato, Pieter De Wit, Elie Maricau, Georges G. E. Gielen:
Offset measurement method for accurate characterization of BTI-induced degradation in opamps. ICECS 2012: 661-664 - 2011
- [j70]Elie Maricau, Georges G. E. Gielen:
Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(1): 50-58 (2011) - [j69]Bo Liu, Francisco V. Fernández, Georges G. E. Gielen:
Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 793-805 (2011) - [j68]Bo Liu, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen:
Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(10): 1458-1468 (2011) - [j67]Athanasios Stefanou, Georges G. E. Gielen:
A Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to Substrate Noise Coupling. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 877-881 (2011) - [j66]Bart De Vuyst, Pieter Rombouts, Georges G. E. Gielen:
A Rigorous Approach to the Robust Design of Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(12): 2829-2837 (2011) - [j65]Trent McConaghy, Pieter Palmers, Michiel Steyaert, Georges G. E. Gielen:
Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks. IEEE Trans. Evol. Comput. 15(4): 557-570 (2011) - [c169]Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene:
A 0.6V to 1.6V, 46μW voltage and temperature independent 48 MHz pulsed LC oscillator for RFID tags. A-SSCC 2011: 109-112 - [c168]Xinpeng Xing, Maarten De Bock, Pieter Rombouts, Georges G. E. Gielen:
A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS. A-SSCC 2011: 249-252 - [c167]Carolina Mora Lopez, Silke Musa, Carmen Bartic, Robert Puers, Georges G. E. Gielen, Wolfgang Eberle:
Systematic design of a programmable low-noise CMOS neural interface for cell activity recording. DATE 2011: 818-823 - [c166]Bo Liu, Ying He, Patrick Reynaert, Georges G. E. Gielen:
Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model. DATE 2011: 1101-1106 - [c165]Elie Maricau, Georges G. E. Gielen:
Stochastic circuit reliability analysis. DATE 2011: 1285-1290 - [c164]Georges G. E. Gielen, Elie Maricau, Pieter De Wit:
Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation. DATE 2011: 1474-1479 - [c163]Elie Maricau, Georges G. E. Gielen:
Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelines. ESSCIRC 2011: 243-246 - [c162]Pieter De Wit, Georges G. E. Gielen:
A failure-resilient xDSL line driver with on-chip degradation monitor. ESSCIRC 2011: 247-250 - [c161]Hans Danneels, Kristof Coddens, Georges G. E. Gielen:
A fully-digital, 0.3V, 270 nW capacitive sensor interface without external references. ESSCIRC 2011: 287-290 - [c160]Dimitri de Jonghe, Georges G. E. Gielen:
Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories. ICCAD 2011: 91-94 - [c159]Simon Vanden Bussche, Pieter De Wit, Elie Maricau, Georges G. E. Gielen:
Impact analysis of stochastic transistor aging on current-steering DACs in 32nm CMOS. ICECS 2011: 161-164 - [c158]Bo Liu, Murat Pak, Xuezhi Zheng, Georges G. E. Gielen:
A novel operating-point driven method for the sizing of analog IC. ISCAS 2011: 781-784 - [c157]Wim Dehaene, Georges G. E. Gielen, Geert Deconinck, Johan Driesen, Marc Moonen, Bart Nauwelaers, Chris Van Hoof, Patrick Wambacq:
Circuits and systems engineering education through interdisciplinary team-based design projects. ISCAS 2011: 1195-1198 - [c156]Carolina Mora Lopez, Dries Braeken, Carmen Bartic, Robert Puers, Georges G. E. Gielen, Wolfgang Eberle:
A 16-channel low-noise programmable system for the recording of neural signals. ISCAS 2011: 1451-1454 - 2010
- [j64]Zheng Li, Georges G. E. Gielen:
Energy Normalized Correlation for Signal Acquisition in Power-Control-Absent UWB Networks. IEEE Commun. Lett. 14(7): 653-655 (2010) - [j63]Nick Van Helleputte, Marian Verhelst, Wim Dehaene, Georges G. E. Gielen:
A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging. IEEE J. Solid State Circuits 45(1): 69-83 (2010) - [j62]Soheil Radiom, Majid Baghaei Nejad, Karim Aghdam, Guy A. E. Vandenbosch, Li-Rong Zheng, Georges G. E. Gielen:
Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-μm Standard CMOS. IEEE J. Solid State Circuits 45(9): 1746-1758 (2010) - [j61]Elie Maricau, Georges G. E. Gielen:
Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1884-1893 (2010) - [j60]Bart De Vuyst, Pieter Rombouts, Jeroen De Maeyer, Georges G. E. Gielen:
The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time SigmaDelta Modulators. IEEE Trans. Circuits Syst. II Express Briefs 57-II(6): 416-420 (2010) - [c155]Bo Liu, Francisco V. Fernández, Qingfu Zhang, Murat Pak, Suha Sipahi, Georges G. E. Gielen:
An enhanced MOEA/D-DE and its application to multiobjective analog cell sizing. IEEE Congress on Evolutionary Computation 2010: 1-7 - [c154]Elie Maricau, Georges G. E. Gielen:
Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity. DATE 2010: 1094-1099 - [c153]Bo Liu, Francisco V. Fernández, Georges G. E. Gielen:
An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique. DATE 2010: 1106-1111 - [c152]Georges G. E. Gielen, Elie Maricau, Pieter De Wit:
Design automation towards reliable analog integrated circuits. ICCAD 2010: 248-251 - [c151]Pieter De Wit, Georges G. E. Gielen:
Efficient simulation model for DAC dynamic properties. ISCAS 2010: 2896-2899 - [c150]Wouter Volkaerts, Bart Marien, Hans Danneels, Valentijn De Smedt, Patrick Reynaert, Wim Dehaene, Georges G. E. Gielen:
A 0.5 V-1.4 V supply-independent frequency-based analog-to-digital converter with fast start-up time for wireless sensor networks. ISCAS 2010: 3096-3099
2000 – 2009
- 2009
- [j59]Ewout Martens, Georges G. E. Gielen:
ANTIGONE: Top-down creation of analog-to-digital converter architectures. Integr. 42(1): 10-23 (2009) - [j58]Nick Van Helleputte, Georges G. E. Gielen:
A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers. IEEE J. Solid State Circuits 44(7): 1862-1871 (2009) - [j57]Trent McConaghy, Georges G. E. Gielen:
Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1162-1175 (2009) - [j56]Trent McConaghy, Pieter Palmers, Michiel Steyaert, Georges G. E. Gielen:
Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1281-1294 (2009) - [j55]Trent McConaghy, Georges G. E. Gielen:
Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1627-1640 (2009) - [j54]Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca:
A memetic approach to the automatic design of high-performance analog integrated circuits. ACM Trans. Design Autom. Electr. Syst. 14(3): 42:1-42:24 (2009) - [j53]Zheng Li, Wim Dehaene, Georges G. E. Gielen:
A 3-tier UWB-based indoor localization system for ultra-low-power sensor networks. IEEE Trans. Wirel. Commun. 8(6): 2813-2818 (2009) - [c149]Bo Liu, Francisco V. Fernández, Georges G. E. Gielen:
Fuzzy selection based differential evolution algorithm for analog cell sizing capturing imprecise human intentions. IEEE Congress on Evolutionary Computation 2009: 622-629 - [c148]Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong:
Guess, solder, measure, repeat: how do I get my mixed-signal chip right? DAC 2009: 520-521 - [c147]Pieter Palmers, Trent McConaghy, Michiel Steyaert, Georges G. E. Gielen:
Massively multi-topology sizing of analog integrated circuits. DATE 2009: 706-711 - [c146]Wolfgang Eberle, Ashwin S. Mecheri, Thi Kim Thoa Nguyen, Georges G. E. Gielen, Raymond Campagnolo, Alison J. Burdett, Chris Toumazou, Bart Volckaerts:
Health-care electronics The market, the challenges, the progress. DATE 2009: 1030-1034 - [c145]Elie Maricau, Georges G. E. Gielen:
Efficient reliability simulation of analog ICs including variability and time-varying stress. DATE 2009: 1238-1241 - [c144]Yi Ke, Jan Craninckx, Georges G. E. Gielen:
A design methodology for fully reconfigurable Delta-Sigma data converters. DATE 2009: 1379-1384 - [c143]Georges G. E. Gielen:
Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS. DDECS 2009: 1 - [c142]Mohammad Masoumi, Erik Markert, Ulrich Heinkel, Georges G. E. Gielen:
Ultra low power flash ADC for UWB transceiver applications. ECCTD 2009: 41-44 - [c141]Bo Liu, Francisco V. Fernández, Peng Gao, Georges G. E. Gielen:
A fuzzy selection based constraint handling method for multi-objective optimization of analog cells. ECCTD 2009: 611-614 - [c140]Athanasios Stefanou, Georges G. E. Gielen:
Mitigation of the sampling and substrate noise induced distortion in regenerative comparators by adaptive interpolation. ECCTD 2009: 631-634 - [c139]Georges G. E. Gielen, Dimitri de Jonghe, Johan Loeckx:
Towards automated extraction of EMC-aware trajectory-based macromodels for analog circuits. ECCTD 2009: 763-766 - [c138]Wim Dehaene, Georges G. E. Gielen, Michiel Steyaert, Hans Danneels, V. Desmedt, Christophe De Roover, Z. Li, Marian Verhelst, Nick Van Helleputte, S. Radioma, C. Walravensa, L. Pleysier:
RFID, where are they? ESSCIRC 2009: 36-43 - [c137]Valentijn De Smedt, Wim Dehaene, Georges G. E. Gielen:
A 0.4-1.4V 24MHz fully integrated 33µW, 104ppm/V supply-independent oscillator for RFIDs. ESSCIRC 2009: 396-399 - [c136]Ivick Guerra-Gómez, Esteban Tlelo-Cuautle, Trent McConaghy, Georges G. E. Gielen:
Optimizing current conveyors by evolutionary algorithms including differential evolution. ICECS 2009: 259-262 - [c135]Bo Liu, Francisco V. Fernández, Dimitri de Jonghe, Georges G. E. Gielen:
Less expensive and high quality stopping criteria for MC-based analog IC yield optimization. ICECS 2009: 267-270 - [c134]Elie Maricau, Georges G. E. Gielen:
A methodology for measuring transistor ageing effects towards accurate reliability simulation. IOLTS 2009: 21-26 - [c133]Athanasios Stefanou, Georges G. E. Gielen:
Prediction of Non-uniform Sampling Distortion Due to Substrate Noise Coupling in Regenerative Comparators. ISCAS 2009: 968-971 - [c132]Majid Baghaei Nejad, David S. Mendoza, Zhuo Zou, Soheil Radiom, Georges G. E. Gielen, Li-Rong Zheng, Hannu Tenhunen:
A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOS. ISSCC 2009: 198-199 - [c131]Marian Verhelst, Nick Van Helleputte, Georges G. E. Gielen, Wim Dehaene:
A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging. ISSCC 2009: 250-251 - 2008
- [j52]Minghu Jiang, Georges G. E. Gielen:
Analysis of quantization effects on high-order function neural networks. Appl. Intell. 28(1): 51-67 (2008) - [j51]Ewout Martens, Georges G. E. Gielen:
Classification of analog synthesis tools based on their architecture selection mechanisms. Integr. 41(2): 238-252 (2008) - [j50]Elie Maricau, Pieter De Wit, Georges G. E. Gielen:
An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications. Microelectron. Reliab. 48(8-9): 1576-1580 (2008) - [j49]Yi Ke, Jan Craninckx, Georges G. E. Gielen:
A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios. IEEE Trans. Circuits Syst. II Express Briefs 55-II(3): 229-233 (2008) - [c130]David M. Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury:
From Transistor to PLL - Analogue Design and EDA Methods. DATE 2008 - [c129]Georges G. E. Gielen, Pieter De Wit, Elie Maricau, Johan Loeckx, Javier Martín-Martínez, Ben Kaczer, Guido Groeseneken, Rosana Rodríguez, Montserrat Nafría:
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. DATE 2008: 1322-1327 - [c128]Nick Van Helleputte, Georges G. E. Gielen:
A 46pJ/pulse analog front-end in 130nm CMOS for UWB impulse radio receivers. ESSCIRC 2008: 378-381 - [c127]Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert:
Automated extraction of expert knowledge in analog topology selection and sizing. ICCAD 2008: 392-395 - [c126]Peng Gao, Trent McConaghy, Georges G. E. Gielen:
Importance sampled circuit learning ensembles for robust analog IC design. ICCAD 2008: 396-399 - [c125]Peng Gao, Trent McConaghy, Georges G. E. Gielen:
ISCLEs: Importance Sampled Circuit Learning Ensembles for Trustworthy Analog Circuit Topology Synthesis. ICES 2008: 11-21 - [c124]Hans Danneels, Marian Verhelst, Pieter Palmers, Wim Vereecken, Bruno Boury, Wim Dehaene, Michiel Steyaert, Georges G. E. Gielen:
A low-power mixing DAC IR-UWB-receiver. ISCAS 2008: 2697-2700 - 2007
- [j48]Tao Chen, Georges G. E. Gielen:
A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration. IEEE J. Solid State Circuits 42(11): 2386-2394 (2007) - [j47]Rob A. Rutenbar, Georges G. E. Gielen, Jaijeet S. Roychowdhury:
Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs. Proc. IEEE 95(3): 640-669 (2007) - [j46]Georges G. E. Gielen, Donatella Sciuto:
Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 405-407 (2007) - [j45]Tao Chen, Georges G. E. Gielen:
The Analysis and Improvement of a Current-Steering DAC's Dynamic SFDR - II: The Output-Dependent Delay Differences. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(2): 268-279 (2007) - [c123]Georges G. E. Gielen:
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies. ASP-DAC 2007: 432-437 - [c122]Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert:
Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies. DAC 2007: 944-947 - [c121]Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen:
An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection. DATE 2007: 81-86 - [c120]Georges G. E. Gielen, Tom Eeckelaert, Ewout Martens, Trent McConaghy:
Automated synthesis of complex analog circuits. ECCTD 2007: 20-23 - [c119]Athanasios Stefanou, Georges G. E. Gielen:
Analyzing the performance degradation of flash A/D converters due to substrate noise coupling. ECCTD 2007: 360-363 - [c118]Georges G. E. Gielen:
Future trends for wireless communication frontends in nanometer CMOS. ACM Great Lakes Symposium on VLSI 2007: 600-605 - [c117]Yi Ke, Soheil Radiom, Hamidreza Rezaee, Guy A. E. Vandenbosch, Jan Craninckx, Georges G. E. Gielen:
Optimal Design Methodology for High-Order Continuous-Time Wideband Delta-Sigma Converters. ICECS 2007: 743-746 - [c116]Athanasios Stefanou, Georges G. E. Gielen:
Effect of Mismatch on Substrate Noise Coupling on Flash A/D Converters. ICECS 2007: 1228-1231 - [c115]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941 - [e3]Georges G. E. Gielen:
2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007. IEEE Computer Society 2007, ISBN 1-4244-1382-6 [contents] - [i2]Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen:
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming. CoRR abs/0710.4630 (2007) - [i1]Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich:
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? CoRR abs/0710.4709 (2007) - 2006
- [j44]Ewout Martens, Georges G. E. Gielen:
Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 924-932 (2006) - [j43]Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1146-1154 (2006) - [j42]Tao Chen, Georges G. E. Gielen:
The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(1): 3-15 (2006) - [j41]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2): 296-305 (2006) - [j40]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 23-33 (2006) - [c114]Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen:
Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard. DAC 2006: 25-30 - [c113]Trent McConaghy, Georges G. E. Gielen:
Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns. DATE 2006: 269-274 - [c112]Ewout Martens, Georges G. E. Gielen:
Top-down heterogeneous synthesis of analog and mixed-signal systems. DATE 2006: 275-280 - [c111]Ewout Martens, Georges G. E. Gielen:
Generic Behavioral Modeling of Analog and Mixed-Signal Systems. FDL 2006: 15-23 - [c110]Trent McConaghy, Georges G. E. Gielen:
Canonical form functions as a simple means for genetic programming to evolve human-interpretable functions. GECCO 2006: 855-862 - [c109]Trent McConaghy, Georges G. E. Gielen:
Automation in mixed-signal design: challenges and solutions in the wake of the nano era. ICCAD 2006: 461-463 - [c108]Raf Schoofs, Tom Eeckelaert, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology. ICECS 2006: 950-953 - [c107]Alkis A. Hatzopoulos, Stefanos Stefanou, Georges G. E. Gielen, Dominique Schreurs:
Assessment of parameter extraction methods for integrated inductor design and model validation. ISCAS 2006 - [c106]Ewout Martens, Georges G. E. Gielen:
A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers. ISCAS 2006 - [e2]Georges G. E. Gielen:
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006. European Design and Automation Association, Leuven, Belgium 2006, ISBN 3-9810801-0-6 [contents] - [e1]Georges G. E. Gielen:
Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006. European Design and Automation Association, Leuven, Belgium 2006, ISBN 3-9810801-1-4 [contents] - 2005
- [j39]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1): 65-76 (2005) - [j38]João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert:
An Efficient, Fully Parasitic-Aware Power Amplifier Design Optimization Tool. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8): 1526-1534 (2005) - [c105]Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen:
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. ASP-DAC 2005: 230-235 - [c104]Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert:
Performance space modeling for hierarchical synthesis of analog integrated circuits. DAC 2005: 881-886 - [c103]Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich:
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? DATE 2005: 36-42 - [c102]Ewout Martens, Georges G. E. Gielen:
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series. DATE 2005: 120-125 - [c101]Tom Eeckelaert, Trent McConaghy, Georges G. E. Gielen:
Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces. DATE 2005: 1070-1075 - [c100]Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen:
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming. DATE 2005: 1082-1087 - [c99]Alkis A. Hatzopoulos, Stefanos Stefanou, Georges G. E. Gielen, Dominique Schreurs:
Analysis of coil parameter extraction methods for on-chip inductor design. ECCTD 2005: 39-42 - [c98]Martin Vogels, Georges G. E. Gielen:
Systematic top-down design of A/D converters. ECCTD 2005: 293-296 - [c97]Didier Van Reeth, Georges G. E. Gielen:
A design automation tool for low-power signal filters for use in sensor interfaces. ECCTD 2005: 433-436 - [c96]Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen:
CAFFEINE: template-free symbolic model generation of analog circuits via canonical form functions and genetic programming. ESSCIRC 2005: 243-246 - [c95]Trent McConaghy, Georges G. E. Gielen:
Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization. ISCAS (2) 2005: 1298-1301 - [c94]Ewout Martens, Georges G. E. Gielen:
Behavioral modeling and simulation of weakly nonlinear sampled-data systems. ISCAS (3) 2005: 2247-2250 - [c93]Trent McConaghy, Georges G. E. Gielen:
IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming. ISCAS (5) 2005: 5170-5173 - [c92]Didier Van Reeth, Georges G. E. Gielen:
A CAD Platform for Sensor Interfaces in Low-Power Applications. PATMOS 2005: 374-381 - 2004
- [j37]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits 39(7): 1119-1130 (2004) - [j36]Georges G. E. Gielen, Kenneth Francken, Ewout Martens, Martin Vogels:
An analytical integration method for the simulation of continuous-time ΔΣ modulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 389-399 (2004) - [j35]Ovidiu Bajdechi, Georges G. E. Gielen, Johan H. Huijsing:
Systematic design exploration of delta-sigma ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 86-95 (2004) - [j34]Jurgen Deveugele, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 191-195 (2004) - [j33]Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Efficient analysis of slow-varying oscillator dynamics. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(8): 1457-1467 (2004) - [c91]Ewout Martens, Georges G. E. Gielen:
High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models. ASP-DAC 2004: 51-56 - [c90]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC 2004: 501-504 - [c89]Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC 2004: 854-859 - [c88]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE 2004: 88-93 - [c87]Ewout Martens, Georges G. E. Gielen:
A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design. DATE 2004: 436-441 - [c86]Tholom Kiely, Georges G. E. Gielen:
Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines. DATE 2004: 448-453 - [c85]Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen:
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. DATE 2004: 604-609 - [c84]Tao Chen, Peter Geens, Geert Van der Plas, Wim Dehaene, Georges G. E. Gielen:
A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL. ESSCIRC 2004: 167-170 - [c83]Tao Chen, Georges G. E. Gielen:
Modelling of the impact of the current source output impedance on the SFDR of current-steering CMOS D/A converters. ISCAS (1) 2004: 293-296 - [c82]João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert:
Knowledge- and optimization-based design of RF power amplifiers. ISCAS (1) 2004: 629-632 - [c81]Minghu Jiang, Georges G. E. Gielen:
Backpropagation Analysis of the Limited Precision on High-Order Function Neural Networks. ISNN (1) 2004: 305-310 - [c80]Minghu Jiang, Dafan Liu, Beixing Deng, Georges G. E. Gielen:
A Bayesian Classifier by Using the Adaptive Construct Algorithm of the RBF Networks. ISNN (1) 2004: 876-881 - 2003
- [j32]Minghu Jiang, Georges G. E. Gielen, Bo Zhang, Zhensheng Luo:
Fast Learning Algorithms for Feedforward Neural Networks. Appl. Intell. 18(1): 37-54 (2003) - [j31]Minghu Jiang, Georges G. E. Gielen:
The Effects of Quantization on Multi-Layer Feedforward Neural Networks. Int. J. Pattern Recognit. Artif. Intell. 17(4): 637-661 (2003) - [j30]Koen Uyttenhove, Jan Vandenbussche, Erik Lauwers, Georges G. E. Gielen, Michiel S. J. Steyaert:
Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter. IEEE J. Solid State Circuits 38(3): 483-494 (2003) - [j29]Mustafa Badaroglu, Stéphane Donnay, Hugo J. De Man, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell:
Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies. IEEE J. Solid State Circuits 38(7): 1250-1260 (2003) - [j28]H. Alan Mantooth, Georges G. E. Gielen:
Guest editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2): 121-123 (2003) - [j27]Bart De Smedt, Georges G. E. Gielen:
WATSON: design space boundary exploration and model generation for analog and RFIC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2): 213-224 (2003) - [j26]Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 517-534 (2003) - [j25]Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Behavioral modeling of (coupled) harmonic oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1017-1026 (2003) - [j24]Kenneth Francken, Georges G. E. Gielen:
A high-level simulation and synthesis environment for ΔΣ modulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1049-1061 (2003) - [j23]Walter Daems, Bart De Smedt, Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen, Hugo De Man:
PeopleMover: an example of interdisciplinary project-based education in electrical engineering. IEEE Trans. Educ. 46(1): 157-167 (2003) - [c79]Martin Vogels, Georges G. E. Gielen:
Architectural selection of A/D converters. DAC 2003: 974-977 - [c78]Ewout Martens, Georges G. E. Gielen:
A Model of Computation for Continuous-Time ?-? Modulators. DATE 2003: 10162-10167 - [c77]Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors. DATE 2003: 10238-10243 - [c76]Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Generalized Posynomial Performance Modeling. DATE 2003: 10250-10255 - [c75]Bart De Smedt, Georges G. E. Gielen:
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits. DATE 2003: 10256-10263 - [c74]Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. DATE 2003: 10642-10649 - [c73]Martin Vogels, Georges G. E. Gielen:
Figure of Merit Based Selection of A/D Converters. DATE 2003: 11090-11091 - [c72]Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen:
Modelling impact of digital substrate noise on embedded regenerative comparators. ESSCIRC 2003: 253-256 - [c71]Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC 2003: 257-260 - [c70]Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
A Generalized Method for Computing Oscillator Phase Noise Spectra. ICCAD 2003: 247-250 - [c69]Tao Chen, Georges G. E. Gielen:
Analysis of the dynamic SFDR property of high-accuracy current-steering D/A converters. ISCAS (1) 2003: 973-976 - 2002
- [j22]Minghu Jiang, Xiaoyan Zhu, Georges G. E. Gielen, Elliott Drábek, Ying Xia, Gang Tan, Ta Bao:
Braille to print translations for Chinese. Inf. Softw. Technol. 44(2): 91-100 (2002) - [j21]Georges G. E. Gielen:
Editorial. Integr. 33(1-2): 1-2 (2002) - [j20]Minghu Jiang, Georges G. E. Gielen, Beixing Deng, Xiaoyan Zhu:
A fast learning algorithm for time-delay neural networks. Inf. Sci. 148(1-4): 27-39 (2002) - [j19]Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. IEEE J. Solid State Circuits 37(8): 1065-1072 (2002) - [j18]Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, John Compiet, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. IEEE J. Solid State Circuits 37(11): 1383-1395 (2002) - [j17]Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Circuit simplification for the symbolic analysis of analogintegrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 395-407 (2002) - [j16]Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen:
A layout synthesis methodology for array-type analog blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 645-661 (2002) - [j15]Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1011-1024 (2002) - [j14]Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
CYCLONE: automated design and layout of RF LC-oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1161-1170 (2002) - [j13]Erik Lauwers, Georges G. E. Gielen:
Power estimation methods for analog circuits for architectural exploration of integrated systems. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 155-162 (2002) - [c68]Bart De Smedt, Georges G. E. Gielen:
WATSON: a multi-objective design space exploration tool for analog and RF IC design. CICC 2002: 31-34 - [c67]Jan Vandenbussche, Koen Uyttenhove, Erik Lauwers, Michel S. J. Steyaert, Georges G. E. Gielen:
A 8-bit 200 MS/s interpolating/averaging CMOS A/D converter. CICC 2002: 445-448 - [c66]Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen:
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC 2002: 399-404 - [c65]Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits. DAC 2002: 431-436 - [c64]Ovidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen:
Optimal design of delta-sigma ADCs by design space exploration. DAC 2002: 443-448 - [c63]Jan Vandenbussche, Koen Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen:
Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter. DAC 2002: 449-454 - [c62]Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Behavioral modeling of (coupled) harmonic oscillators. DAC 2002: 536-541 - [c61]Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics. DATE 2002: 268-273 - [c60]Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices. DATE 2002: 279-284 - [c59]Jan Vandenbussche, Erik Lauwers, Koen Uyttenhove, Michiel Steyaert, Georges G. E. Gielen:
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter. DATE 2002: 357-361 - [c58]Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen:
DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators. DATE 2002: 1110 - [c57]Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
On the difference between two widely publicized methods for analyzing oscillator phase behavior. ICCAD 2002: 229-233 - [c56]Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen:
A behavioral simulation tool for continuous-time delta sigma modulators. ICCAD 2002: 234-239 - [c55]Ovidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen:
Power optimization in ΣΔ ADC design. DSP 2002: 353-359 - [c54]Francky Leyn, Erik Lauwers, Martin Vogels, Georges G. E. Gielen, Willy M. C. Sansen:
Regression criteria and their application in different modeling cases. ISCAS (5) 2002: 85-8 - [c53]Martin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen:
Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration. ISCAS (4) 2002: 237-240 - 2001
- [j12]Erik Lauwers, Jan Suls, Walter Gumbrecht, David Maes, Georges G. E. Gielen, Willy Sansen:
A CMOS multiparameter biochemical microsensor with temperature control and signal interfacing. IEEE J. Solid State Circuits 36(12): 2030-2038 (2001) - [j11]Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts:
AMGIE-A synthesis environment for CMOS analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1037-1058 (2001) - [c52]Kenneth Francken, Martin Vogels, Georges G. E. Gielen:
Dedicated system-level simulation of ΔΣ modulators. CICC 2001: 349-352 - [c51]Wim Verhaegen, Georges G. E. Gielen:
Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits. DAC 2001: 139-144 - [c50]Georges G. E. Gielen, Mike Sottak, Mike Murray, Linda Kaye, Maria del Mar Hershenson, Kenneth S. Kundert, Philippe Magarshack, Akria Matsuzawa, Ronald A. Rohrer, Ping Yang:
Panel: When Will the Analog Design Flow Catch Up with Digital Methodology? DAC 2001: 419 - [c49]Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model. DATE 2001: 169-175 - [c48]Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens:
High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE 2001: 326-330 - [c47]Georges G. E. Gielen:
Design challenges and emerging EDA solutions in mixed-signal IC design. DATE 2001: 694-695 - [c46]Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing. ICCAD 2001: 70-74 - [c45]Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen:
Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. ICCAD 2001 - [c44]Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
A Layout-Aware Synthesis Methodology for RF Circuits. ICCAD 2001: 358- - 2000
- [j10]Georges G. E. Gielen, Rob A. Rutenbar:
Computer-aided design of analog and mixed-signal integrated circuits. Proc. IEEE 88(12): 1825-1854 (2000) - [c43]Martin Vogels, Bart De Smedt, Georges G. E. Gielen:
Modeling and Simulation of a Sigma-Delta Digital to Analog Converter Using VHDL-AMS. BMAS 2000: 5-9 - [c42]Erik Lauwers, Georges G. E. Gielen, Koen Lampaert, Paolo Miliozzi:
High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A. BMAS 2000: 16-21 - [c41]Peter J. Vancorenland, Carl De Ranter, Michiel Steyaert, Georges G. E. Gielen:
Optimal RF design using smart evolutionary algorithms. DAC 2000: 7-10 - [c40]Carl De Ranter, Bram De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
CYCLONE: automated design and layout of RF LC-oscillators. DAC 2000: 11-14 - [c39]Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen:
Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. DAC 2000: 452-457 - [c38]Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy:
Survival strategies for mixed-signal systems-on-chip (panel session). DAC 2000: 579-580 - [c37]Kenneth Francken, Peter J. Vancorenland, Georges G. E. Gielen:
DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators. ICCAD 2000: 188-192 - [c36]Erik Lauwers, Georges G. E. Gielen:
ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters. ICCAD 2000: 193-196 - [c35]Martin Vogels, Georges G. E. Gielen:
Efficient analysis of the stability of sigma-delta modulators using wavelets. ISCAS 2000: 764-
1990 – 1999
- 1999
- [j9]Geert Van der Plas, Jan Vandenbussche, Willy Sansen, Michel S. J. Steyaert, Georges G. E. Gielen:
A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE J. Solid State Circuits 34(12): 1708-1718 (1999) - [c34]Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits. DAC 1999: 958-963 - [c33]Erik Lauwers, Georges G. E. Gielen:
A Power Estimation Model for High-Speed CMOS A/D Converters. DATE 1999: 401-405 - [c32]Piet Wambacq, Gerd Vandersteen, Stéphane Donnay, Marc Engels, Ivo Bolsens, Erik Lauwers, Piet Vanassche, Georges G. E. Gielen:
High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications. ICECS 1999: 525-528 - [c31]Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels, Ivo Bolsens, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell:
BANDIT: embedding analog-to-digital converters on digital telecom ASICs. ICECS 1999: 1377-1380 - [c30]Geert Van der Plas, Jan Vandenbussche, Wim Verhaegen, Georges G. E. Gielen, Willy Sansen:
Statistical behavioral modeling for A/D-converters. ICECS 1999: 1713-1716 - [c29]Kenneth Francken, Georges G. E. Gielen:
Methodology for analog technology porting including performance tuning. ISCAS (1) 1999: 415-418 - 1998
- [j8]Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen:
High-Level Power Minimization of Analog Sensor Interface Architectures. Integr. Comput. Aided Eng. 5(4): 303-314 (1998) - [j7]Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen:
Probabilistic fault detection and the selection of measurements for analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 862-872 (1998) - [c28]Bart De Smedt, Georges G. E. Gielen:
Nonlinear behavioral modeling and phase noise evaluation in phase locked loops. CICC 1998: 53-56 - [c27]Anne Van den Bosch, Marc Borremans, Jan Vandenbussche, Geert Van der Plas, Augusto Manuel Marques, José Bastos, Michiel Steyaert, Georges G. E. Gielen, Willy Sansen:
A 12 bit 200 MHz low glitch CMOS D/A converter. CICC 1998: 249-252 - [c26]Georges G. E. Gielen:
Modeling and simulation for low power in mixed-signal integrated systems. CICC 1998: 445-449 - [c25]Francky Leyn, Willy Sansen, Georges G. E. Gielen:
Transforming small-signal modeling into control system modeling. CICC 1998: 469-472 - [c24]Jan Vandenbussche, Geert Van der Plas, Georges G. E. Gielen, Michiel Steyaert, Willy Sansen:
Behavioral model for D/A converters as VSI virtual components. CICC 1998: 473-476 - [c23]Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy Sansen:
Mondriaan: a tool for automated layout synthesis of array-type analog blocks. CICC 1998: 485-488 - [c22]Jan Vandenbussche, Stéphane Donnay, Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen:
Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon. DATE 1998: 716-720 - [c21]Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen:
An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits. ICCAD 1998: 304-307 - [c20]Geert Debyser, Georges G. E. Gielen:
Efficient analog circuit synthesis with simultaneous yield and robustness optimization. ICCAD 1998: 308-311 - [c19]Wim Verhaegen, Georges G. E. Gielen:
Efficient symbolic analysis of analog integrated circuits using determinant decision diagrams. ICECS 1998: 89-92 - 1997
- [c18]Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts, W. van Bokhoven:
High-level synthesis of analog sensor interface front-ends. ED&TC 1997: 56-60 - [c17]Francky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps. ICCAD 1997: 374-381 - [c16]Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen:
Automated test pattern generation for analog integrated circuits. VTS 1997: 296-301 - 1996
- [c15]L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen:
Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. DAC 1996: 298-303 - [c14]Philippe Reynaert, Ludwig G. A. Callewaert, Georges G. E. Gielen, Geert Debyser, Koen Lampaert, Francky Leyn, Geert Van der Plas, Willy Sansen, Birger Schneider, René Bloch, Dave Orton, Steve Boardman, Jeremy Stent, Jean-François Agaësse, Jörg-Olliver Fischer-Binder, Jukka Riihiaho, Kari Tukkiniemi:
ADMIRE: advanced mixed signal design environment. ICECS 1996: 428-431 - 1995
- [j6]Georges G. E. Gielen, Geert Debyser, Koen Lampaert, Francky Leyn, Koen Swings, Geert Van der Plas, Willy Sansen, Domine Leenaerts, Petar Veselinovic, W. van Bokhoven:
An analogue module generator for mixed analogue/digital asic design. Int. J. Circuit Theory Appl. 23(4): 269-283 (1995) - [j5]Piet Wambacq, Francisco V. Fernández, Georges G. E. Gielen, Willy Sansen, Ángel Rodríguez-Vázquez:
Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits. IEEE J. Solid State Circuits 30(3): 327-330 (1995) - [j4]Koen Lampaert, Georges G. E. Gielen, Willy M. C. Sansen:
A performance-driven placement tool for analog integrated circuits. IEEE J. Solid State Circuits 30(7): 773-780 (1995) - [c13]Koen Lampaert, Georges G. E. Gielen, Willy M. C. Sansen:
Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits. DAC 1995: 445-449 - [c12]Petar Veselinovic, Domine Leenaerts, W. van Bokhoven, Francky Leyn, F. Proesmans, Georges G. E. Gielen, Willy Sansen:
A flexible topology selection program as part of an analog synthesis system. ED&TC 1995: 119-125 - [c11]Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen:
A high-level design and optimization tool for analog RF receiver front-ends. ICCAD 1995: 550-553 - [c10]Georges G. E. Gielen, Geert Debyser, Piet Wambacq, Koen Swings, Willy M. C. Sansen:
Use of Symbolic Analysis in Analog Circuit Synthesis. ISCAS 1995: 2205-2208 - 1994
- [j3]Georges G. E. Gielen, Piet Wambacq, Willy M. C. Sansen:
Symbolic analysis methods and applications for analog circuits: a tutorial overview. Proc. IEEE 82(2): 287-304 (1994) - [c9]Stéphane Donnay, Koen Swings, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts:
A Methodology for Analog Design Automation in Mixed-Signal ASICs. EDAC-ETC-EUROASIC 1994: 530-534 - [c8]Georges G. E. Gielen, Zhihua Wang, Willy M. C. Sansen:
Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring. ICCAD 1994: 495-498 - [c7]Francisco V. Fernández, Piet Wambacq, Georges G. E. Gielen, Ángel Rodríguez-Vázquez, Willy M. C. Sansen:
Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation. ISCAS 1994: 25-28 - [c6]Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen:
A Novel Method for the Fault Detection of Analog Integrated Circuits. ISCAS 1994: 347-350 - [c5]Francisco V. Fernández, Georges G. E. Gielen, Lawrence Huelsman, Agnieszka Konczykowska, Stefano Manetti, Willy M. C. Sansen, Jirí Vlach:
Pleasures, Perils and Pitfalls of Symbolic Analysis. ISCAS 1994: 451-457 - 1993
- [c4]Georges G. E. Gielen, Willy M. C. Sansen:
Modeling of the Power-supply Interactions of CMOS Operational Amplifiers Using Symbolic Computation. ISCAS 1993: 1381-1384 - 1991
- [b1]Georges G. E. Gielen, Willy M. C. Sansen:
Symbolic analysis for automated design of analog integrated circuits. The Kluwer international series in engineering and computer science 137, Kluwer 1991, ISBN 978-0-7923-9161-6, pp. I-XII, 1-290 - [c3]Piet Wambacq, Georges G. E. Gielen, Willy Sansen:
Interactive symbolic distortion analysis of analogue integrated circuits. EURO-DAC 1991: 484-488 - [c2]Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli, Georges G. E. Gielen, Paul R. Gray:
A Behavioral Representation for Nyquist Rate A/D Converters. ICCAD 1991: 386-389 - 1990
- [j2]Georges G. E. Gielen, Herman C. C. Walscharts, Willy M. C. Sansen:
Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE J. Solid State Circuits 25(3): 707-713 (1990) - [c1]Georges G. E. Gielen, Koen Swings, Willy M. C. Sansen:
An intelligent design system for analogue integrated circuits. EURO-DAC 1990: 169-173
1980 – 1989
- 1989
- [j1]Georges G. E. Gielen, Herman C. C. Walscharts, Willy M. C. Sansen:
ISAAC: a symbolic simulator for analog integrated circuits. IEEE J. Solid State Circuits 24(6): 1587-1597 (1989)
Coauthor Index
Hugo De Man
aka: Hugo J. De Man
aka: Hugo J. De Man
Willy M. C. Sansen
aka: Willy Sansen
aka: Willy Sansen
[c121] [c114] [c108] [j34] [j33] [j29] [j26] [j25] [j23] [c77] [c76] [c72] [c70] [j17] [j16] [j15] [j14] [c65] [c62] [c61] [c60] [c57] [c54] [j12] [j11] [c49] [c46] [c44] [c40] [c39] [j9] [c34] [c31] [c30] [j8] [j7] [c27] [c25] [c24] [c23] [c22] [c21] [c18] [c17] [c15] [c14] [j6] [j5] [j4] [c13] [c12] [c10] [j3] [c9] [c8] [c7] [c6] [c5] [c4] [b1] [c3] [j2] [c1] [j1]
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