"Scalable Gate-Level Models for Power and Timing Analysis."

Mustafa Badaroglu et al. (2007)

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DOI: 10.1109/ISCAS.2007.377865

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941

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