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ORCIDFábio Luís Livi Ramos
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2020 – today
- 2024
[c12]Gabriel Bitencourt Cardoso, Daniel Felipe Tomm, Jiovana Sousa Gomes, Rodrigo N. Wuerdig, Sergio Bampi, Fábio Luís Livi Ramos:
Statistical Analysis of VVC Residual and Entropy Coding aiming Efficient Hardware Design. LASCAS 2024: 1-5- 2023
- [c11]Jiovana Sousa Gomes, Tulio Pereira Bitencourt
, Sergio Bampi, Fábio Luís Livi Ramos:
Analysis of AV1 Arithmetic Decoder Design Space with a Novel Multi-Boolean Approach. LASCAS 2023: 1-4 - [c10]Jiovana Sousa Gomes, Rodrigo N. Wuerdig, Fábio Luís Livi Ramos, Sergio Bampi:
AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture. SBCCI 2023: 1-6 - 2022
- [j4]Jiovana Sousa Gomes, Tulio Pereira Bitencourt, Sergio Bampi, Fábio Luís Livi Ramos:
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder. IEEE Des. Test 39(6): 119-127 (2022) - [j3]Tulio Pereira Bitencourt, Fábio Luís Livi Ramos, Sergio Bampi:
Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture. IEEE Des. Test 39(6): 128-137 (2022) - [c9]Jiovana Sousa Gomes, Tulio Pereira Bitencourt, Sergio Bampi, Fábio Luís Livi Ramos:
Area and Power Efficient 8K Real-Time Design for AV1 Arithmetic Decoding. PCS 2022: 7-11 - [c8]Tulio Pereira Bitencourt, Fábio Luís Livi Ramos, Sergio Bampi:
Power-Throughput Trade-off Analysis for a Novel Multi-Boolean AV1 Arithmetic Encoder Design. PCS 2022: 25-29 - 2021
- [j2]Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
Energy-Throughput Configurable Design for Video Processing Binary Arithmetic Encoder. IEEE Trans. Circuits Syst. Video Technol. 31(3): 1163-1177 (2021) - 2020
- [j1]Fábio Luís Livi Ramos, Alessandro Via Piana Saggiorato, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
Residual Syntax Elements Analysis and Design Targeting High-Throughput HEVC CABAC. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 475-488 (2020)
2010 – 2019
- 2018
- [c7]Alessandro Via Piana Saggiorato, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
HEVC Residual Syntax Elements Generation Architecture for High-Throughput CABAC Design. ICECS 2018: 193-196 - [c6]Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
High-Throughput Binary Arithmetic Encoder using Multiple-Bypass Bins Processing for HEVC CABAC. ISCAS 2018: 1-5 - 2017
- [c5]Camila de Matos Alonso, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing. SBCCI 2017: 30-35 - [c4]Luana Vieira Martinez Bonatto, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
Low-power multi-size HEVC DCT architecture proposal for QFHD video processing. SBCCI 2017: 41-46 - [c3]Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture. SBCCI 2017: 47-52 - 2016
- [c2]Fábio Luís Livi Ramos, Jones Goebel, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi:
Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos. SBCCI 2016: 1-6 - 2010
- [c1]Fábio Luís Livi Ramos, Bruno Zatt, Thaísa Leal da Silva, Altamiro Amadeu Susin, Sergio Bampi:
A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding. ICECS 2010: 587-590
Coauthor Index
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