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2020 – today
- 2024
[j108]Sehee Lim
, Junghyeon Hwang, Dong Han Ko, Se Keon Kim, Tae Woo Oh, Sanghun Jeon, Seong-Ook Jung:
Design of Physically Unclonable Function Using Ferroelectric FET With Auto Write-Back Technique for Resource-Limited IoT Security. IEEE Internet Things J. 11(16): 27676-27686 (2024)- [j107]Sekeon Kim, Sehee Lim, Dong Han Ko, Tae Woo Oh, Seong-Ook Jung:
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 274-286 (2024) - [j106]Hong Keun Ahn, Sumin Lee, Seong-Ook Jung:
A CNN-Based Super-Resolution Processor With Short-Term Caching for Real-Time UHD Upscaling. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1198-1207 (2024) - [j105]In Jun Jung, Do Han Kim, Minyoung Jo, Dong Han Ko, Young Kyu Lee, Seong-Ook Jung:
A Charge-Domain 4T2C eDRAM Compute-in-Memory Macro With Enhanced Variation Tolerance and Low-Overhead Data Conversion Schemes. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1824-1828 (2024) - [j104]Young Kyu Lee, Dong Han Ko, Seokhee Cho, Minjune Yeo, Mingu Kang, Seong-Ook Jung:
Split WL 6T SRAM-Based Bit Serial Computing-in-Memory Macro With High Signal Margin and High Throughput. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1869-1873 (2024) - [j103]Tae-Hyun Kim, Juhyun Park, In Jun Jung, Hoonki Kim, Taejoong Song, Seong-Ook Jung:
A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs. IEEE Trans. Circuits Syst. II Express Briefs 71(10): 4531-4535 (2024) - [c50]Giseok Kim, Jaehyun Park, Seong-Ook Jung:
Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization. ICEIC 2024: 1-3 - [c49]Minjune Yeo, Keonhee Cho, Giseok Kim, Won Joon Jo, Jisang Oh, Sekeon Kim, Kyeongrim Baek, Sungho Park, Seung Jae Yei, Seong-Ook Jung:
15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node. ISSCC 2024: 282-284 - 2023
- [j102]Sehee Lim, Youngin Goh, Young Kyu Lee, Dong Han Ko, Junghyeon Hwang, Yeongseok Jeong, Hunbeom Shin, Sanghun Jeon, Seong-Ook Jung:
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices. IEEE J. Solid State Circuits 58(7): 1860-1870 (2023) - [j101]Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung:
An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s. IEEE J. Solid State Circuits 58(11): 3242-3252 (2023) - [j100]Sehee Lim, Dong Han Ko, Se Keon Kim, Seong-Ook Jung:
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 806-818 (2023) - [j99]Tae Woo Oh, Juhyun Park, Tae Hyun Kim, Keonhee Cho, Seong-Ook Jung:
Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 306-310 (2023) - [j98]Taeyun Lee, In Jun Jung, Seong-Ook Jung:
High-Precision and Low-Power Offset Canceling Tri-State Sensing Latch in NAND Flash Memory. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2325-2329 (2023) - [j97]In Jun Jung, Tae-Hyun Kim, Keonhee Cho, Ki-Ryong Kim, Seong-Ook Jung:
An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3243-3247 (2023) - [c48]Sekeon Kim, Keonhee Cho, Kyeongrim Baek, Hyunjun Kim, Younmee Bae, Mijung Kim, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung:
A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. VLSI Technology and Circuits 2023: 1-2 - [c47]Taeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung:
A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j96]Keonhee Cho, Heekyung Choi, In Jun Jung, Ji Sang Oh, Tae Woo Oh, Ki-Ryong Kim, Giseok Kim, Taemin Choi, Changsu Sim, Taejoong Song, Seong-Ook Jung:
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling. IEEE J. Solid State Circuits 57(4): 1039-1048 (2022) - [j95]Ji-Young Kim, Jongsoo Lee, Ki-Ryong Kim, Sunghwan Jo, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung:
A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC. IEEE J. Solid State Circuits 57(6): 1913-1923 (2022) - [j94]Tae-Hyun Kim, Byungkyu Song, In Jun Jung, Seong-Ook Jung:
A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1583-1594 (2022) - [j93]Keonhee Cho, Juhyun Park, Ki-Ryong Kim, Tae Woo Oh, Seong-Ook Jung:
SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1567-1571 (2022) - [c46]Sumin Lee, Ki-Beom Lee, Sunghwan Joo, Hong Keun Ahn, Junghyup Lee, Dohyung Kim, Bumsub Ham, Seong-Ook Jung:
SIF-NPU: A 28nm 3.48 TOPS/W 0.25 TOPS/mm2 CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-Resolution. ESSCIRC 2022: 97-100 - [c45]Sehee Lim, Youngin Goh, Young Kyu Lee, Dong Han Ko, Junghyeon Hwang, Minki Kim, Yeongseok Jeong, Hunbeom Shin, Sanghun Jeon, Seong-Ook Jung:
A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF. ESSCIRC 2022: 113-116 - [c44]Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung:
A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM. VLSI Technology and Circuits 2022: 152-153 - [c43]Keonhee Cho, Giseok Kim, Ji Sang Oh, Ki-Ryong Kim, Changsu Sim, Younmee Bae, Mijung Kim, Sangyeop Baeck, Taejoong Song, Seong-Ook Jung:
A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications. VLSI Technology and Circuits 2022: 214-215 - 2021
- [j92]Jun Ho An, Jin Young Chun, Hyun Kook Park, Seong-Ook Jung:
All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash. IEEE Access 9: 28001-28011 (2021) - [j91]Se Keon Kim, Tae Woo Oh, Sehee Lim, Dong Han Ko, Seong-Ook Jung:
High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops. IEEE Access 9: 35549-35561 (2021) - [j90]Ki-Ryong Kim, Tae Woo Oh, Seong-Ook Jung:
Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM. IEEE Access 9: 57393-57403 (2021) - [j89]Ji Sang Oh, Juhyun Park, Keonhee Cho, Tae Woo Oh, Seong-Ook Jung:
Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation. IEEE Access 9: 64105-64115 (2021) - [j88]Dong Han Ko, Tae Woo Oh, Sehee Lim, Se Keon Kim, Seong-Ook Jung:
Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells. IEEE Access 9: 127895-127905 (2021) - [j87]Hanwool Jeong, Tae Hyun Kim, Changnam Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung:
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. IEEE J. Solid State Circuits 56(2): 554-565 (2021) - [j86]Sara Choi, Hong Keun Ahn, Byungkyu Song, Seung-Hyuk Kang, Seong-Ook Jung:
Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6): 2481-2493 (2021) - [j85]Suk Min Kim, Byungkyu Song, Seong-Ook Jung:
Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6): 2546-2554 (2021) - [j84]Taehui Na, Seung-Hyuk Kang, Seong-Ook Jung:
STT-MRAM Sensing: A Review. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 12-18 (2021) - [j83]Ki-Ryong Kim, Ji Young Kim, Byoung-Mo Moon, Seong-Ook Jung:
A 6.9-μm2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1433-1437 (2021) - [j82]Ji-Young Kim, Jongsoo Lee, Ki-Ryong Kim, Byoung-Mo Moon, Seong-Ook Jung:
A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface With VOH Drift Control. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1822-1826 (2021) - [j81]Byungkyu Song, Sehee Lim, Seung-Hyuk Kang, Seong-Ook Jung:
Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell With Auto Write-Back Technique. IEEE Trans. Inf. Forensics Secur. 16: 2843-2853 (2021) - [j80]Kwang Woo Lee, Hyun Kook Park, Seong-Ook Jung:
Adaptive Sensing Voltage Modulation Technique in Cross-Point OTS-PRAM. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 631-642 (2021) - [c42]Dong Han Ko, Sehee Lim, Young Kyu Lee, Seong-Ook Jung:
High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit. ISOCC 2021: 321-322 - [c41]Ki Beom Lee, Sumin Lee, Sunghwan Joo, Hong Keun Ahn, Young Seok Jung, Seong-Ook Jung:
CNN encryption using XOR Gate for Hardware Optimization. ISOCC 2021: 359-360 - [c40]Young Kyu Lee, Minjune Yeo, Seokhee Cho, Seong-Ook Jung:
Intrinsic Capacitance based Multi bit Computing in Memory. ISOCC 2021: 361-362 - [c39]Keonhee Cho, Heekyung Choi, In Jun Jung, Ji Sang Oh, Tae Woo Oh, Ki-Ryong Kim, Giseok Kim, Taemin Choi, Changsoo Sim, Taejoong Song, Seong-Ook Jung:
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. VLSI Circuits 2021: 1-2 - 2020
- [j79]Tae Hyun Kim, Hanwool Jeong, Juhyun Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung:
An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache. IEEE Access 8: 187126-187139 (2020) - [j78]Sumin Lee, Sunghwan Jo, Hong Keun Ahn, Seong-Ook Jung:
CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution. IEEE Access 8: 187754-187765 (2020) - [j77]Giseok Kim, Ki-Ryong Kim, Sara Choi, Hyo Jung Jang, Seong-Ook Jung:
Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC. IEEE Access 8: 216922-216932 (2020) - [j76]Jongha Park, Jung-Hyun Park, Seong-Ook Jung:
Current Measurement Transducer Based on Current-To-Voltage-To-Frequency Converting Ring Oscillator with Cascade Bias Circuit. Sensors 20(2): 493 (2020) - [j75]Keonhee Cho, Juhyun Park, Tae Woo Oh, Seong-Ook Jung:
One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1551-1561 (2020) - [j74]Sehee Lim, Byungkyu Song, Seong-Ook Jung:
Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability. IEEE Trans. Inf. Forensics Secur. 15: 2798-2807 (2020) - [j73]Juhyun Park, Tae Woo Oh, Seong-Ook Jung:
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1079-1083 (2020) - [j72]Hyun Kook Park, Hong Keun Ahn, Seong-Ook Jung:
A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2650-2657 (2020) - [c38]Kwang Woo Lee, Hyun Kook Park, Seong-Ook Jung:
A Read Voltage Modulation Technique for Leakage Current Compensation in Cross-Point OTS-PRAM. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j71]Hanwool Jeong, Se Hyeok Oh, Tae Woo Oh, Hoonki Kim, Changnam Park, Woojin Rim, Taejoong Song, Seong-Ook Jung:
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving. IEEE J. Solid State Circuits 54(3): 896-906 (2019) - [j70]Hanwool Jeong, Juhyun Park, Seung Chul Song, Seong-Ook Jung:
Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time. IEEE J. Solid State Circuits 54(8): 2304-2315 (2019) - [j69]Byungkyu Song, Sara Choi, Seung-Hyuk Kang, Seong-Ook Jung:
Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2963-2972 (2019) - [j68]Sara Choi, Hong Keun Ahn, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 387-397 (2019) - [j67]Junyoung Ko, Younghwi Yang, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim, Seong-Ook Jung:
Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1828-1839 (2019) - [j66]Suk Min Kim, Byungkyu Song, Seong-Ook Jung:
Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2413-2422 (2019) - [j65]Taehui Na, Byungkyu Song, Sara Choi, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2548-2555 (2019) - 2018
- [j64]Dong-Hoon Jung, Ki-Ryong Kim, Sunghwan Jo, Seong-Ook Jung:
0.293-mm2 Fast Transient Response Hysteretic Quasi-V2 DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-µm CMOS. IEEE J. Solid State Circuits 53(6): 1844-1855 (2018) - [j63]Taehui Na, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 163-174 (2018) - [j62]Hanwool Jeong, Tae Woo Oh, Seung Chul Song, Seong-Ook Jung:
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 609-620 (2018) - [j61]Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung:
All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1015-1025 (2018) - [c37]Hyun Kook Park, Tae Woo Oh, Seong-Ook Jung:
A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation. ICECS 2018: 273-276 - [c36]Beomsang Yoo, Ki-Ryong Kim, Seong-Ook Jung:
Triplet-based Spike Timing Dependent Plasticity Circuit Design for three-terminal Spintronic Synapse. ICECS 2018: 689-692 - [c35]Tae Woo Oh, Seong-Ook Jung:
SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation. ISCAS 2018: 1-4 - [c34]Suk Min Kim, Byungkyu Song, Tae Woo Oh, Seong-Ook Jung:
Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM. PRIME 2018: 65-68 - 2017
- [j60]Jung-Hyun Park, Dong-Hoon Jung, Seong-Ook Jung:
GRO-TDC with gate-switch-based delay cell halving resolution limit. Int. J. Circuit Theory Appl. 45(12): 2211-2225 (2017) - [j59]Taehui Na, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS. IEEE J. Solid State Circuits 52(2): 496-504 (2017) - [j58]Byungkyu Song, Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 700-704 (2017) - [j57]Junyoung Ko, Younghwi Yang, Jisu Kim, Younghoon Oh, Hyun Kook Park, Seong-Ook Jung:
Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6): 1444-1455 (2017) - [j56]Tae Hoon Choi, Hanwool Jeong, Younghwi Yang, Juhyun Park, Seong-Ook Jung:
SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 2063-2072 (2017) - [j55]Tae Woo Oh, Hanwool Jeong, Juhyun Park, Seong-Ook Jung:
Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2737-2747 (2017) - [j54]Tae Woo Oh, Hanwool Jeong, Kyoman Kang, Juhyun Park, Younghwi Yang, Seong-Ook Jung:
Power-Gated 9T SRAM Cell for Low-Energy Operation. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1183-1187 (2017) - 2016
- [j53]Dong-Hoon Jung, Ki-Ryong Kim, Seong-Ook Jung:
Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm. IEICE Electron. Express 13(12): 20160287 (2016) - [j52]Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. II Express Briefs 63-II(6): 578-582 (2016) - [j51]Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung:
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7): 1023-1032 (2016) - [j50]Ki-Ryong Kim, Hanwool Jeong, Juhyun Park, Seong-Ook Jung:
Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 964-968 (2016) - [j49]Hanwool Jeong, Juhyun Park, Tae Woo Oh, Woojin Rim, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1059-1063 (2016) - [j48]Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung:
All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1015-1024 (2016) - [j47]Kyoman Kang, Hanwool Jeong, Younghwi Yang, Juhyun Park, Ki-Ryong Kim, Seong-Ook Jung:
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1342-1350 (2016) - [j46]Taehui Na, Jisu Kim, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1361-1370 (2016) - [j45]Kyungho Ryu, Jiwan Jung, Dong-Hoon Jung, Jin Hyuk Kim, Seong-Ook Jung:
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1484-1492 (2016) - [j44]Sara Choi, Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2851-2860 (2016) - [j43]Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2993-2997 (2016) - [j42]Young-Jae An, Dong-Hoon Jung, Kyungho Ryu, Hyuck-Sang Yim, Seong-Ook Jung:
All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3232-3242 (2016) - [c33]Junyoung Ko, Younghwi Yang, Seong-Ook Jung, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim:
WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. ISCAS 2016: 1022-1025 - [c32]Sara Choi, Taehui Na, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang:
Area-optimal sensing circuit designs in deep submicrometer STT-RAM. ISCAS 2016: 1246-1249 - [c31]Beomsang Yoo, Taehui Na, Byungkyu Song, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang:
Equalization scheme analysis for high-density spin transfer torque random access memory. ISOCC 2016: 99-100 - 2015
- [j41]Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, Sudeb Dasgupta, Seong-Ook Jung:
Low power SRAM design for 14 nm GAA Si-nanowire technology. Microelectron. J. 46(12): 1239-1247 (2015) - [j40]Hanwool Jeong, Taewon Kim, Younghwi Yang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1062-1070 (2015) - [j39]Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung:
SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1538-1545 (2015) - [j38]Hanwool Jeong, Taewon Kim, Kyoman Kang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1555-1563 (2015) - [j37]Byungkyu Song, Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1776-1784 (2015) - [j36]Junyoung Ko, Jisu Kim, Youngdon Choi, Hyun Kook Park, Seong-Ook Jung:
Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2091-2102 (2015) - [j35]Dong-Hoon Jung, Young-Jae An, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung:
All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1023-1027 (2015) - [j34]Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory. IEEE Trans. Circuits Syst. II Express Briefs 62-II(12): 1109-1113 (2015) - [j33]Jung-Hyun Park, Heechai Kang, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung:
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 413-421 (2015) - [j32]Heechai Kang, Jisu Kim, Hanwool Jeong, Younghwi Yang, Seong-Ook Jung:
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 752-765 (2015) - [j31]Hanwool Jeong, Taewon Kim, Taejoong Song, Gyu-Hong Kim, Seong-Ook Jung:
Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1370-1374 (2015) - [j30]Young-Jae An, Dong-Hoon Jung, Kyungho Ryu, Seung-Han Woo, Seong-Ook Jung:
An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1508-1517 (2015) - [j29]Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung:
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2748-2752 (2015) - [c30]Taehui Na, Hanwool Jeong, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang:
Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter. ICECS 2015: 400-403 - [c29]Byungkyu Song, Taehui Na, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang:
Reference-circuit analysis for high-bandwidth spin transfer torque random access memory. ISLPED 2015: 365-370 - 2014
- [j28]Youngdon Jung, Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
An MTJ-based non-volatile flip-flop for high-performance SoC. Int. J. Circuit Theory Appl. 42(4): 394-406 (2014) - [j27]Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung:
Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector. IEEE Trans. Circuits Syst. II Express Briefs 61-II(1): 1-5 (2014) - [j26]Jisu Kim, Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A Split-Path Sensing Circuit for Spin Torque Transfer MRAM. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 193-197 (2014) - [j25]Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3376-3385 (2014) - [j24]Taehui Na, Seung-Han Woo, Jisu Kim, Hanwool Jeong, Seong-Ook Jung:
Comparative Study of Various Latch-Type Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 425-429 (2014) - [j23]Hanwool Jeong, Younghwi Yang, Junha Lee, Jisu Kim, Seong-Ook Jung:
One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1262-1269 (2014) - [j22]Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1620-1624 (2014) - [j21]Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1630-1634 (2014) - [c28]Hanwool Jeong, Taewon Kim, Seong-Ook Jung, Taejoong Song, Gyu-Hong Kim:
Pseudo NMOS based sense amplifier for high speed single-ended SRAM. ICECS 2014: 331-334 - [c27]Taehui Na, Kyungho Ryu, Jisu Kim, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang:
High-performance low-power magnetic tunnel junction based non-volatile flip-flop. ISCAS 2014: 1953-1956 - 2013
- [j20]Mingu Kang, Jisu Kim, Younghwi Yang, Seong-Ook Jung:
Dynamic mixed serial-parallel content addressable memory (DMSP CAM). Int. J. Circuit Theory Appl. 41(7): 721-731 (2013) - [j19]Jung-Hyun Park, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung:
ADDLL for Clock-Deskew Buffer in High-Performance SoCs. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1368-1373 (2013) - [c26]Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Won Lee, Seong-Ook Jung:
All-digital 90° phase-shift DLL with a dithering jitter suppression scheme. CICC 2013: 1-4 - [c25]Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung:
All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. ESSCIRC 2013: 41-44 - [c24]Young-Jae An, Kyungho Ryu, Dong-Hoon Jung, Seung-Han Woo, Seong-Ook Jung:
A 0.67nJ/S time-domain temperature sensor for low power on-chip thermal management. ICCE 2013: 572-573 - [c23]Taehui Na, Kyungho Ryu, Jisu Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A comparative study of STT-MTJ based non-volatile flip-flops. ISCAS 2013: 109-112 - 2012
- [j18]Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung:
A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1860-1870 (2012) - [j17]Heechai Kang, Kyungho Ryu, Dong-Hoon Jung, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung:
Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2186-2196 (2012) - [j16]Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung:
A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM). IEEE Trans. Very Large Scale Integr. Syst. 20(1): 181-186 (2012) - [j15]Kyungho Ryu, Jisu Kim, Jiwan Jung, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2044-2053 (2012) - [c22]Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung:
A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. ESSCIRC 2012: 181-184 - [c21]Hanwool Jeong, Younghwi Yang, Junha Lee, Jisu Kim, Seong-Ook Jung:
Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits. ICECS 2012: 833-836 - [c20]Jaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyungho Ryu, Dong-Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong-Ook Jung, Woo-Young Choi, Sungho Kang:
Integration of dual channel timing formatter system for high speed memory test equipment. ISOCC 2012: 185-187 - [c19]Junha Lee, Hanwool Jeong, Younghwi Yang, Jisu Kim, Seong-Ook Jung:
Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM. ISOCC 2012: 479-482 - 2011
- [j14]Jee-Hwan Song, Jisu Kim, Seung-Hyuk Kang, Sei-Seung Yoon, Seong-Ook Jung:
Sensing margin trend with technology scaling in MRAM. Int. J. Circuit Theory Appl. 39(3): 313-325 (2011) - [c18]Youngdon Jung, Jisu Kim, Kyungho Ryu, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang:
MTJ based non-volatile flip-flop in deep submicron technology. ISOCC 2011: 424-427 - 2010
- [j13]Jisu Kim, Jee-Hwan Song, Seung-Hyuk Kang, Sei-Seung Yoon, Seong-Ook Jung:
Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits. IEICE Trans. Electron. 93-C(6): 912-921 (2010) - [j12]Kyungho Ryu, Dong Hun Jung, Seong-Ook Jung:
A DLL based clock generator for low-power mobile SoCs. IEEE Trans. Consumer Electron. 56(3): 1950-1956 (2010) - [j11]Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung:
A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface. IEEE Trans. Consumer Electron. 56(4): 2400-2405 (2010) - [c17]Heechai Kang, Kyungho Ryu, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung:
Process variation tolerant all-digital multiphase DLL for DDR3 interface. CICC 2010: 1-4
2000 – 2009
- 2009
- [j10]Mingu Kang, Seong-Ook Jung:
Serial-Parallel Content Addressable Memory with a Conditional Driver (SPCwCD). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(1): 318-321 (2009) - [j9]Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy:
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(7): 1428-1441 (2009) - 2008
- [j8]Seong-Ook Jung, Sei-Seung Yoon:
Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(3): 895-898 (2008) - [j7]Hyunwoo Nho, Sei-Seung Yoon, S. Simon Wong, Seong-Ook Jung:
Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 907-911 (2008) - 2007
- [c16]Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy:
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. ISLPED 2007: 387-390 - 2006
- [c15]Rich Roy, Farid Nemati, Ken Young, Bruce Bateman, Rajesh Chopra, Seong-Ook Jung, Chiming Show, Hyun-Jin Cho:
Thyristor-Based Volatile Memory in Nano-Scale CMOS. ISSCC 2006: 2612-2621 - 2005
- [j6]Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang:
A 32-bit carry lookahead adder using dual-path all-N logic. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 992-996 (2005) - 2004
- [c14]Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang:
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. ISCAS (2) 2004: 781-784 - 2003
- [j5]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Timing constraints for domino logic gates with timing-dependent keepers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 96-103 (2003) - [j4]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang:
Minimum delay optimization for domino circuits - a coupling-aware approach. ACM Trans. Design Autom. Electr. Syst. 8(2): 202-213 (2003) - [j3]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 79-89 (2003) - [j2]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang:
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 879-887 (2003) - 2002
- [b1]Seong-Ook Jung:
Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology. University of Illinois Urbana-Champaign, USA, 2002 - [j1]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Noise constrained transistor sizing and power optimization for dual Vst domino logic. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 532-541 (2002) - [c13]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Low-swing clock domino logic incorporating dual supply and dual threshold voltages. DAC 2002: 467-472 - [c12]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. DATE 2002: 260-265 - [c11]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Optimal Timing for Skew-Tolerant High-Speed Domino Logic. ISVLSI 2002: 41-46 - 2001
- [c10]Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737 - [c9]Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang:
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. ACM Great Lakes Symposium on VLSI 2001: 93-96 - [c8]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Transistor sizing for reliable domino logic design in dual threshold voltage technologies. ACM Great Lakes Symposium on VLSI 2001: 133-138 - [c7]Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang:
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. ISCAS (4) 2001: 1-4 - [c6]Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang:
Skew-tolerant high-speed (STHS) domino logic. ISCAS (4) 2001: 154-157 - [c5]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Noise constrained power optimization for dual VT domino logic. ISCAS (4) 2001: 158-161 - [c4]Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang:
Coupling-aware minimum delay optimization for domino logic circuits. ISCAS (5) 2001: 371-374 - [c3]Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
New current-mode sense amplifiers for high density DRAM and PIM architectures. ISCAS (4) 2001: 938-941 - 2000
- [c2]Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic. ISCAS 2000: 756-759 - [c1]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware power optimization for on-chip interconnect. ISLPED 2000: 108-113
Coauthor Index
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