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ORCIDUnni Narayanan
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2000 – 2009
- 2003
[j2]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 79-89 (2003)- 2002
- [c8]Unni Narayanan, Ki-Seok Chung, Taewhan Kim:
Enhanced bus invert encodings for low-power. ISCAS (5) 2002: 25-28 - 2000
- [j1]Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung:
Decomposition of Bus-Invert Coding for Low-Power I/O. J. Circuits Syst. Comput. 10(1-2): 101-112 (2000) - [c7]Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang:
Domino logic synthesis minimizing crosstalk. DAC 2000: 280-285 - [c6]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware power optimization for on-chip interconnect. ISLPED 2000: 108-113
1990 – 1999
- 1999
- [c5]Priyadarshan Patra
, Unni Narayanan:
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits. DAC 1999: 379-384 - [c4]Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy:
Characterizing Individual Gate Power Sensitivity in Low Power Design. VLSI Design 1999: 625- - 1998
- [b1]Unni Narayanan:
Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits. University of Illinois Urbana-Champaign, USA, 1998 - [c3]Unni Narayanan, Peichen Pan, C. L. Liu:
Low power logic synthesis under a general delay model. ISLPED 1998: 209-214 - 1997
- [c2]Unni Narayanan, C. L. Liu:
Low power logic synthesis for XOR based circuits. ICCAD 1997: 570-574 - [c1]Unni Narayanan, Hon Wai Leong, Ki-Seok Chung, Chien-Liang Liu:
Low power multiplexer decomposition. ISLPED 1997: 269-274
Coauthor Index
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