"Low power logic synthesis under a general delay model."

Unni Narayanan, Peichen Pan, C. L. Liu (1998)

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DOI: 10.1145/280756.280900

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/islped/NarayananPL98
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Unni Narayanan, Peichen Pan, C. L. Liu:
Low power logic synthesis under a general delay model. ISLPED 1998: 209-214

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